- 14 Jun, 2020 1 commit
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Raptor Engineering Development Team authored
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- 13 Jun, 2020 1 commit
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Raptor Engineering Development Team authored
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- 09 Jun, 2020 9 commits
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Raptor Engineering Development Team authored
Add external control line to either hold off or start IPL based on contol line status
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
This is required to interface with certain hardware, such as the IBM POWER9. Without some delay added, the FSI interface on the POWER9 processor will send invalid responses and generally malfunction.
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Raptor Engineering Development Team authored
This is required due to the extra input register on both FSI master and slave. Without the extra turnaround time, stale data from the TAR period can trigger spurious START signals. As before, this value is not provided in the specification, but appears to fall well below actual TAR times as observed on IBM POWER9 hardware.
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 08 Jun, 2020 9 commits
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Raptor Engineering Development Team authored
Add flag to support undocumented extended address (23-bit address) mode in both FSI master and slave Add external configuration interface for FSI slave ID
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
This value is not provided in the specification, but appears to fall well below actual TAR times as observed on IBM POWER9 hardware. Extending to two clock cycles allows the bus to stabilize after tristating has completed.
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
This was discovered and verified with physical IBM POWER9 hardware, as the OpenFSI specification is silent on the format of the relative address offset.
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- 07 Jun, 2020 4 commits
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Raptor Engineering Development Team authored
Fix FSI slave parsing of REL_ADR address fields
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Raptor Engineering Development Team authored
This avoids potentially transmitting stale data on fast back to back reads
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
Adjust FSI master and slave core state machines to use more compact bitwise encoding Add internal debug port to FSI master
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- 05 Jun, 2020 6 commits
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Raptor Engineering Development Team authored
This core implements the (relatively poorly documented) OpenFSI 1.0.0 specification available from the OpenPOWER Foundation. As with the FSI master core, considerable uncertainty exists surrounding error recovery and whether any extant FSI slaves honor error recovery actions undertaken during I_POLL command processing, thus error recovery is controlled by two independent enable bits in case incomaptible slaves are enountered in the wild.
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
Invert FSI data in signal to match electrical interface specification
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Raptor Engineering Development Team authored
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- 04 Jun, 2020 1 commit
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Raptor Engineering Development Team authored
This core implements the (relatively poorly documented) OpenFSI 1.0.0 specification available from the OpenPOWER Foundation. Considerable uncertainty exists surrounding error recovery and whether any extant FSI slaves honor error recovery actions undertaken during I_POLL command processing, thus error recovery is controlled by two independent enable bits in case incomaptible slaves are enountered in the wild.
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- 19 May, 2020 1 commit
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Raptor Engineering Development Team authored
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- 11 May, 2020 1 commit
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Raptor Engineering Development Team authored
This significantly speeds up system IPL, and represents the fastest practical IPL speed for this small dual-PLL FPGA. Larger FPGAs such as the quad PLL ECP5 should be able to reach the 100+MHz quad SPI maximum frequency when used with properly laid out PCBs.
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- 10 May, 2020 7 commits
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Raptor Engineering Development Team authored
Switch main sequencer to use word transfer for firmware reads.
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
Use quad SPI I/O for all firmware read cycles. This significantly improves overall IPL speed.
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
This avoids clock domain crossing glitches between the SPI core and the sequencer logic.
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Raptor Engineering Development Team authored
Shave a master clock cycle off the SPI transfer by initiating frame start on transition from idle state
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Raptor Engineering Development Team authored
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