Fix TERM / BREAK handling in master core

parent ec2e5cff
......@@ -171,9 +171,11 @@ module fsi_master_interface(
end
FSI_INITIALIZE_STATE_02: begin
// Send BREAK command
// BREAK is *not* CRC protected!
if (cycle_counter > 0) begin
fsi_data_direction_reg <= 1;
crc_protected_bits_transmitting = 1;
crc_protected_bits_transmitting = 0;
crc_protected_bits_receiving = 0;
fsi_data_reg_internal = 1;
cycle_counter <= cycle_counter - 1;
if (cycle_counter == 1) begin
......@@ -201,6 +203,7 @@ module fsi_master_interface(
&& (enable_ipoll && (commands_since_last_ipoll < FSI_IPOLL_MAX_SEQ_STD_COMMANDS))) begin
commands_since_last_ipoll <= commands_since_last_ipoll + 1;
ipoll_in_process <= 0;
crc_data <= 0;
control_state <= FSI_TRANSFER_STATE_TX01;
end else if ((start_cycle && !start_cycle_prev)
&& (enable_ipoll && (commands_since_last_ipoll < FSI_IPOLL_MAX_SEQ_STD_COMMANDS))) begin
......@@ -494,32 +497,38 @@ module fsi_master_interface(
rx_message_type[0] <= fsi_data_in_internal;
case ({rx_message_type[1], fsi_data_in_internal})
FSI_CODEWORD_RX_MSG_ACK: begin
if (data_direction_reg) begin
// Write -- ACK message
if ((fsi_command_code == FSI_CODEWORD_TX_MSG_TERM_DAT) && (fsi_command_code_length == FSI_CODEWORD_TX_MSG_TERM_LEN)) begin
// TERM command sent -- parse ACK message
cycle_counter <= 4;
control_state <= FSI_TRANSFER_STATE_RX06;
end else begin
// Read -- ACK_D message
case (data_length_reg)
0: begin
// Byte transfer
cycle_counter <= 8;
end
1: begin
// Half word transfer
cycle_counter <= 16;
end
2: begin
// Word transfer
cycle_counter <= 32;
end
default: begin
// Invalid sizes are treated as byte transfers
cycle_counter <= 8;
end
endcase
slave_error_recovery_state <= 0;
control_state <= FSI_TRANSFER_STATE_RX05;
if (data_direction_reg) begin
// Write -- ACK message
cycle_counter <= 4;
control_state <= FSI_TRANSFER_STATE_RX06;
end else begin
// Read -- ACK_D message
case (data_length_reg)
0: begin
// Byte transfer
cycle_counter <= 8;
end
1: begin
// Half word transfer
cycle_counter <= 16;
end
2: begin
// Word transfer
cycle_counter <= 32;
end
default: begin
// Invalid sizes are treated as byte transfers
cycle_counter <= 8;
end
endcase
slave_error_recovery_state <= 0;
control_state <= FSI_TRANSFER_STATE_RX05;
end
end
end
FSI_CODEWORD_RX_MSG_BUSY: begin
......
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