Insert I_POLL as required into long-running D_POLL / BUSY sequences

parent 7a3d39db
......@@ -147,6 +147,7 @@ module fsi_master_interface(
reg [1:0] master_error_recovery_state = 0;
reg [7:0] ipoll_start_timer = 0;
reg ipoll_in_process = 0;
reg busy_response_in_process = 0;
reg [1:0] commands_since_last_ipoll = 0;
reg [1:0] interrupt_field_internal = 0;
reg [2:0] dma_control_field_internal = 0;
......@@ -154,10 +155,16 @@ module fsi_master_interface(
if (peripheral_reset) begin
cycle_complete_reg <= 0;
last_address_valid <= 0;
ipoll_in_process <= 0;
busy_response_in_process <= 0;
control_state <= FSI_INITIALIZE_STATE_01;
end else begin
case (control_state)
FSI_INITIALIZE_STATE_01: begin
// Global (re)-initialization
ipoll_in_process <= 0;
busy_response_in_process <= 0;
// Set up BREAK command
cycle_counter <= FSI_CODEWORD_TX_MSG_BREAK_LEN;
control_state <= FSI_INITIALIZE_STATE_02;
......@@ -190,7 +197,12 @@ module fsi_master_interface(
end
end
FSI_TRANSFER_STATE_IDLE: begin
if (start_cycle && !start_cycle_prev
if (busy_response_in_process
&& (enable_ipoll && (commands_since_last_ipoll < FSI_IPOLL_MAX_SEQ_STD_COMMANDS))) begin
commands_since_last_ipoll <= commands_since_last_ipoll + 1;
ipoll_in_process <= 0;
control_state <= FSI_TRANSFER_STATE_TX01;
end else if ((start_cycle && !start_cycle_prev)
&& (enable_ipoll && (commands_since_last_ipoll < FSI_IPOLL_MAX_SEQ_STD_COMMANDS))) begin
data_direction_reg <= data_direction;
data_length_reg <= data_length;
......@@ -663,8 +675,9 @@ module fsi_master_interface(
fsi_command_code_length <= FSI_CODEWORD_TX_MSG_D_POLL_LEN;
cycle_counter <= FSI_CODEWORD_TX_MSG_D_POLL_LEN;
fsi_command_code_set <= 1;
busy_response_in_process <= 1;
crc_data <= 0;
control_state <= FSI_TRANSFER_STATE_TX01;
control_state <= FSI_TRANSFER_STATE_IDLE;
end else begin
// Send TERM
fsi_command_code <= FSI_CODEWORD_TX_MSG_TERM_DAT;
......@@ -677,6 +690,7 @@ module fsi_master_interface(
end
fsi_master_timeout_counting <= 0;
fsi_command_code_set <= 1;
busy_response_in_process <= 0;
crc_data <= 0;
control_state <= FSI_TRANSFER_STATE_TX01;
end
......@@ -685,6 +699,7 @@ module fsi_master_interface(
if (!ipoll_in_process) begin
cycle_complete_reg <= 1;
end
busy_response_in_process <= 0;
fsi_master_timeout_counting <= 0;
control_state <= FSI_TRANSFER_STATE_TR02;
end
......
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