Add internal debug port to FSI slave

Fix FSI slave parsing of REL_ADR address fields
parent 663d1e42
......@@ -21,6 +21,8 @@ module fsi_slave_interface(
output wire fsi_data_direction, // 0 == tristate (input), 1 == driven (output)
input wire fsi_clock_in,
output wire [7:0] debug_port,
input wire peripheral_reset,
input wire peripheral_clock
);
......@@ -148,6 +150,8 @@ module fsi_slave_interface(
reg [1:0] interrupt_field_reg = 0;
reg [2:0] dma_control_field_reg = 0;
assign debug_port = control_state;
always @(posedge fsi_clock_in) begin
if (peripheral_reset) begin
data_request_strobe_reg <= 0;
......@@ -220,7 +224,7 @@ module fsi_slave_interface(
&& ({fsi_command_code[6:0], fsi_data_in_internal} == FSI_CODEWORD_TX_MSG_REL_ADR_DAT)) begin
fsi_command_code_length <= FSI_CODEWORD_TX_MSG_REL_ADR_LEN;
address_reg <= 0;
cycle_counter <= 9;
cycle_counter <= 8;
control_state <= FSI_TRANSFER_STATE_RX04;
end else if (((cycle_counter + 1) == FSI_CODEWORD_TX_MSG_SAME_ADR_LEN)
&& ({fsi_command_code[6:0], fsi_data_in_internal} == FSI_CODEWORD_TX_MSG_SAME_ADR_DAT)) begin
......
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