Don't lock up FSI master if IPOLL fails

Adjust FSI master and slave core state machines to use more compact bitwise encoding
Add internal debug port to FSI master
parent b6cbcfdf
......@@ -24,6 +24,8 @@ module fsi_master_interface(
output wire fsi_data_direction, // 0 == tristate (input), 1 == driven (output)
output wire fsi_clock_out,
output wire [7:0] debug_port,
input wire peripheral_reset,
input wire peripheral_clock
);
......@@ -68,18 +70,18 @@ module fsi_master_interface(
parameter FSI_INITIALIZE_STATE_01 = 0;
parameter FSI_INITIALIZE_STATE_02 = 1;
parameter FSI_INITIALIZE_STATE_03 = 2;
parameter FSI_TRANSFER_STATE_IDLE = 8;
parameter FSI_TRANSFER_STATE_TX01 = 9;
parameter FSI_TRANSFER_STATE_TX02 = 10;
parameter FSI_TRANSFER_STATE_TX03 = 11;
parameter FSI_TRANSFER_STATE_TX04 = 12;
parameter FSI_TRANSFER_STATE_TX05 = 13;
parameter FSI_TRANSFER_STATE_TX06 = 14;
parameter FSI_TRANSFER_STATE_TX07 = 15;
parameter FSI_TRANSFER_STATE_TX08 = 16;
parameter FSI_TRANSFER_STATE_TX09 = 17;
parameter FSI_TRANSFER_STATE_TX10 = 18;
parameter FSI_TRANSFER_STATE_TX11 = 19;
parameter FSI_TRANSFER_STATE_IDLE = 16;
parameter FSI_TRANSFER_STATE_TX01 = 17;
parameter FSI_TRANSFER_STATE_TX02 = 18;
parameter FSI_TRANSFER_STATE_TX03 = 19;
parameter FSI_TRANSFER_STATE_TX04 = 20;
parameter FSI_TRANSFER_STATE_TX05 = 21;
parameter FSI_TRANSFER_STATE_TX06 = 22;
parameter FSI_TRANSFER_STATE_TX07 = 23;
parameter FSI_TRANSFER_STATE_TX08 = 24;
parameter FSI_TRANSFER_STATE_TX09 = 25;
parameter FSI_TRANSFER_STATE_TX10 = 26;
parameter FSI_TRANSFER_STATE_TX11 = 27;
parameter FSI_TRANSFER_STATE_RX01 = 32;
parameter FSI_TRANSFER_STATE_RX02 = 33;
parameter FSI_TRANSFER_STATE_RX03 = 34;
......@@ -115,7 +117,6 @@ module fsi_master_interface(
assign dma_control_field = dma_control_field_reg;
// Low level protocol handler
reg start_cycle_prev = 0;
reg data_direction_reg = 0;
reg [1:0] data_length_reg = 0;
reg [1:0] slave_id_reg = 0;
......@@ -151,6 +152,9 @@ module fsi_master_interface(
reg [1:0] commands_since_last_ipoll = 0;
reg [1:0] interrupt_field_internal = 0;
reg [2:0] dma_control_field_internal = 0;
assign debug_port = control_state;
always @(posedge peripheral_clock) begin
if (peripheral_reset) begin
cycle_complete_reg <= 0;
......@@ -205,7 +209,7 @@ module fsi_master_interface(
ipoll_in_process <= 0;
crc_data <= 0;
control_state <= FSI_TRANSFER_STATE_TX01;
end else if ((start_cycle && !start_cycle_prev)
end else if (start_cycle
&& (enable_ipoll && (commands_since_last_ipoll < FSI_IPOLL_MAX_SEQ_STD_COMMANDS))) begin
data_direction_reg <= data_direction;
data_length_reg <= data_length;
......@@ -222,6 +226,7 @@ module fsi_master_interface(
slave_error_recovery_state <= 0;
master_error_recovery_state <= 0;
fsi_command_code_set <= 0;
ipoll_in_process <= 0;
crc_data <= 0;
cycle_error_reg <= FSI_ERROR_NONE;
fsi_master_timeout_counting <= 0;
......@@ -727,7 +732,7 @@ module fsi_master_interface(
end
end
FSI_TRANSFER_STATE_TR02: begin
if (!start_cycle) begin
if (!start_cycle || ipoll_in_process) begin
if (cycle_error_reg == FSI_ERROR_NONE) begin
last_address <= address_reg;
last_address_valid <= 1;
......@@ -735,6 +740,7 @@ module fsi_master_interface(
last_address_valid <= 0;
end
ipoll_start_timer <= 0;
ipoll_in_process <= 0;
control_state <= FSI_TRANSFER_STATE_IDLE;
end
end
......@@ -800,6 +806,5 @@ module fsi_master_interface(
end else begin
fsi_master_timeout_counter <= 0;
end
start_cycle_prev <= start_cycle;
end
endmodule
\ No newline at end of file
......@@ -68,16 +68,16 @@ module fsi_slave_interface(
parameter FSI_ERROR_INTERNAL_FAULT = 6;
parameter FSI_TRANSFER_STATE_IDLE = 0;
parameter FSI_TRANSFER_STATE_RX01 = 8;
parameter FSI_TRANSFER_STATE_RX02 = 9;
parameter FSI_TRANSFER_STATE_RX03 = 10;
parameter FSI_TRANSFER_STATE_RX04 = 11;
parameter FSI_TRANSFER_STATE_RX05 = 12;
parameter FSI_TRANSFER_STATE_RX06 = 13;
parameter FSI_TRANSFER_STATE_RX07 = 14;
parameter FSI_TRANSFER_STATE_RX08 = 15;
parameter FSI_TRANSFER_STATE_RX09 = 16;
parameter FSI_TRANSFER_STATE_RX10 = 17;
parameter FSI_TRANSFER_STATE_RX01 = 16;
parameter FSI_TRANSFER_STATE_RX02 = 17;
parameter FSI_TRANSFER_STATE_RX03 = 18;
parameter FSI_TRANSFER_STATE_RX04 = 19;
parameter FSI_TRANSFER_STATE_RX05 = 20;
parameter FSI_TRANSFER_STATE_RX06 = 21;
parameter FSI_TRANSFER_STATE_RX07 = 22;
parameter FSI_TRANSFER_STATE_RX08 = 23;
parameter FSI_TRANSFER_STATE_RX09 = 24;
parameter FSI_TRANSFER_STATE_RX10 = 25;
parameter FSI_TRANSFER_STATE_TR01 = 32;
parameter FSI_TRANSFER_STATE_TR02 = 33;
parameter FSI_TRANSFER_STATE_TX01 = 48;
......
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