Interlock FSI slave data request / ready signals

This avoids potentially transmitting stale data on fast back to back reads
parent 3509486e
......@@ -526,11 +526,13 @@ module fsi_slave_interface(
end
end
FSI_TRANSFER_STATE_TX01: begin
// Send start bit
fsi_data_direction_reg <= 1;
crc_protected_bits_transmitting = 1;
fsi_data_reg_internal = 1;
control_state <= FSI_TRANSFER_STATE_TX02;
if (!data_ready_strobe) begin
// Send start bit
fsi_data_direction_reg <= 1;
crc_protected_bits_transmitting = 1;
fsi_data_reg_internal = 1;
control_state <= FSI_TRANSFER_STATE_TX02;
end
end
FSI_TRANSFER_STATE_TX02: begin
// Send slave ID bit 1
......
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