Adjust addresses to match specified data transfer length per the FSI specification

parent 492b256e
......@@ -8,7 +8,7 @@ module fsi_master_interface(
input wire [20:0] address,
input wire [31:0] tx_data,
output reg [31:0] rx_data,
input wire [1:0] data_length, // 0 == 8 bit, 1 == 16 bit, 2 = 32 bit
input wire [1:0] data_length, // 0 == 8 bit, 1 == 16 bit, 2 = 32 bit (NOTE: the lower two address bits may be forced if 16 bit / 32 bit transfer length is set)
input wire data_direction, // 0 == read from slave, 1 == write to slave
input wire start_cycle,
output wire cycle_complete,
......@@ -214,7 +214,7 @@ module fsi_master_interface(
data_direction_reg <= data_direction;
data_length_reg <= data_length;
slave_id_reg <= slave_id;
case (data_length)
case (data_length_reg)
0: address_reg <= address[20:0];
1: address_reg <= {address[20:1], 1'b0};
2: address_reg <= {address[20:2], 2'b01};
......@@ -359,6 +359,14 @@ module fsi_master_interface(
if (cycle_counter == 1) begin
control_state <= FSI_TRANSFER_STATE_TX07;
end
// Force lowest address bits to specification-mandated values if required
case (data_length_reg)
0: address_tx_reg <= address_tx_reg[20:0];
1: address_tx_reg <= {address_tx_reg[20:1], 1'b0};
2: address_tx_reg <= {address_tx_reg[20:2], 2'b01};
default: address_tx_reg <= address_tx_reg[20:0];
endcase
end else begin
// Should never reach this state
cycle_error_reg <= FSI_ERROR_INTERNAL_FAULT;
......@@ -734,7 +742,7 @@ module fsi_master_interface(
FSI_TRANSFER_STATE_TR02: begin
if (!start_cycle || ipoll_in_process) begin
if (cycle_error_reg == FSI_ERROR_NONE) begin
last_address <= address_reg;
last_address <= address_tx_reg;
last_address_valid <= 1;
end else begin
last_address_valid <= 0;
......
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