Fix LPC clock timing constraints set at double the actual LPC frequency

parent f1b8a6f9
......@@ -18,7 +18,6 @@ ctx.addClock("sequencer_clock", 33)
ctx.addClock("slow_1843khz_uart_clock", 2)
# For some reason both of these clocks are showing up, for presumably different
# sections of the LPC logic. Make sure both can run at DDR speeds versus the
# 33MHz LPC clock, since we use both positive and negative clock edges...
ctx.addClock("lpc_slave_tx_clock_resynthesized", lpc_clock_frequency * 2)
ctx.addClock("lpc_debug_mirror_clock_extern_uart", lpc_clock_frequency * 2)
# sections of the LPC logic. Make sure both can run at LPC speeds.
ctx.addClock("lpc_slave_tx_clock_resynthesized", lpc_clock_frequency)
ctx.addClock("lpc_debug_mirror_clock_extern_uart", lpc_clock_frequency)
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