Signal SPI transaction complete only after any requested dummy cycles have been transmitted

parent 9c66a3ee
......@@ -231,8 +231,8 @@ module spi_master_interface_quad(
end else begin
ss_state_at_idle <= 1'b1;
end
transaction_complete <= 1;
if (dummy_cycle_count_reg == 0) begin
transaction_complete <= 1;
transfer_state <= 3;
end else begin
dummy_cycle_ctr <= 0;
......@@ -287,6 +287,7 @@ module spi_master_interface_quad(
if (dummy_cycle_ctr < dummy_cycle_count_reg) begin
transfer_state <= 4;
end else begin
transaction_complete <= 1;
transfer_state <= 3;
end
......
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