Actually release SPI SS when requested by external control logic

spi_master.v

@@ -53,7 +53,7 @@ module spi_master_interface(
 						transfer_state <= 1;
 					end else begin
 						if (!hold_ss_active_reg) begin
-							ss_state_at_idle <= 1'b0;
+							ss_state_at_idle <= 1'b1;
 						end
 						transfer_state <= 0;
 					end