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Raptor Engineering Public Development
lpc-spi-bridge-fpga
Commits
7a3bacb9
Commit
7a3bacb9
authored
May 09, 2020
by
Raptor Engineering Development Team
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Actually release SPI SS when requested by external control logic
parent
2287d1b7
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spi_master.v
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7a3bacb9
...
...
@@ -53,7 +53,7 @@ module spi_master_interface(
transfer_state
<=
1
;
end
else
begin
if
(
!
hold_ss_active_reg
)
begin
ss_state_at_idle
<=
1'b
0
;
ss_state_at_idle
<=
1'b
1
;
end
transfer_state
<=
0
;
end
...
...
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