Clean up comments in FSI master signal description block

parent 5603ca4e
......@@ -8,8 +8,8 @@ module fsi_master_interface(
input wire [20:0] address,
input wire [31:0] tx_data,
output reg [31:0] rx_data,
input wire [1:0] data_length, // 0 == 8 bit, 1 == 16 bit, 2 = 32 bit
input wire data_direction, // 0 == read from slave, 1 == write to slave
input wire [1:0] data_length, // 0 == 8 bit, 1 == 16 bit, 2 = 32 bit
input wire data_direction, // 0 == read from slave, 1 == write to slave
input wire start_cycle,
output wire cycle_complete,
output wire [2:0] cycle_error,
......@@ -17,9 +17,9 @@ module fsi_master_interface(
input wire enable_ipoll,
output wire ipoll_error,
output wire fsi_data_out, // Must have I/O output register enabled in top level SB_IO or equivalent
output wire fsi_data_out, // Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at falling edge of clock
input wire fsi_data_in,
output wire fsi_data_direction, // 0 == tristate (input), 1 == driven (output)
output wire fsi_data_direction, // 0 == tristate (input), 1 == driven (output)
output wire fsi_clock_out,
input wire peripheral_reset,
......
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