Add write cycle to FSI testbench

parent fd6bee51
......@@ -176,6 +176,19 @@ module fsi_test();
slave_data_ready_strobe = 0;
#282
start_cycle = 0; // End cycle
#48
data_direction = 1; // Drive write request
slave_id = 0; // Absolute addressing since it is outside 256 bytes of the previous transfer address
address = 21'h054321;
tx_data = 32'hf00dface;
data_length = 2; // 32 bit transfer
start_cycle = 1; // Start cycle
#426
slave_data_ready_strobe = 1; // Send response via slave core
#12
slave_data_ready_strobe = 0;
#282
start_cycle = 0; // End cycle
`else
fsi_data_in = 1'b0; // Transmit ACK_D response, 37'b10000011101100101010000110010000100001011
#6
......
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