Initial version of FSI slave and associated testbench

This core implements the (relatively poorly documented) OpenFSI 1.0.0
specification available from the OpenPOWER Foundation.

As with the FSI master core, considerable uncertainty exists surrounding
error recovery and whether any extant FSI slaves honor error recovery
actions undertaken during I_POLL command processing, thus error recovery
is controlled by two independent enable bits in case incomaptible slaves
are enountered in the wild.
parent 73c89d3e
......@@ -19,13 +19,13 @@ lpc_spi_bridge_%.int: lpc_spi_bridge.json timing_constraints.py main.pcf
lpc_spi_bridge.int: lpc_spi_bridge_1.int
cp lpc_spi_bridge_1.int lpc_spi_bridge.int
lpc_spi_bridge.json: main.v lpc_interface.v fsi_master.v spi_master.v ipmi_bt_slave.v flash_block_cache.v simple_rtc.v clock_generator.v $(UART_CORE_FILES)
lpc_spi_bridge.json: main.v lpc_interface.v fsi_master.v fsi_slave.v spi_master.v ipmi_bt_slave.v flash_block_cache.v simple_rtc.v clock_generator.v $(UART_CORE_FILES)
yosys -l yosys.log -q -p "synth_ice40 -top lpc_bridge_top -json lpc_spi_bridge.json" main.v
lpc_spi_bridge.ex: lpc_spi_bridge.int
icebox_explain lpc_spi_bridge.int > lpc_spi_bridge.ex
lpc_spi_bridge_postsynth_sim.blif: main.v lpc_interface.v fsi_master.v spi_master.v ipmi_bt_slave.v flash_block_cache.v simple_rtc.v clock_generator.v $(UART_CORE_FILES) timing_constraints.py main.pcf
lpc_spi_bridge_postsynth_sim.blif: main.v lpc_interface.v fsi_master.v fsi_slave.v spi_master.v ipmi_bt_slave.v flash_block_cache.v simple_rtc.v clock_generator.v $(UART_CORE_FILES) timing_constraints.py main.pcf
yosys -l yosys_postsynth.log -q -f "verilog -DSIMULATION -DPOST_SYNTHESIS" -p "synth_ice40 -top lpc_bridge_top -blif lpc_spi_bridge_postsynth_sim.blif" main.v
lpc_spi_bridge_postsynth_sim.v: lpc_spi_bridge_postsynth_sim.blif
......@@ -61,7 +61,7 @@ dump_toolchain_info:
-@arachne-pnr -v 2>/dev/null
-@echo "================================================================================"
lpc_interface_test.vcd: main.v lpc_interface.v fsi_master.v spi_master.v ipmi_bt_slave.v flash_block_cache.v simple_rtc.v clock_generator.v $(UART_CORE_FILES) testbench_lpc.v
lpc_interface_test.vcd: main.v lpc_interface.v fsi_master.v fsi_slave.v spi_master.v ipmi_bt_slave.v flash_block_cache.v simple_rtc.v clock_generator.v $(UART_CORE_FILES) testbench_lpc.v
rm -f lpc_interface_sim
rm -f lpc_interface_test.vcd
/usr/bin/iverilog -DSIMULATION -o lpc_interface_sim main.v spi_master.v simple_rtc.v clock_generator.v $(UART_CORE_FILES) testbench_lpc.v
......@@ -72,10 +72,10 @@ simulate_lpc: lpc_interface_test.vcd
simulate_lpc_view: lpc_interface_test.vcd
gtkwave lpc_interface_test.vcd
fsi_interface_test.vcd: fsi_master.v testbench_fsi.v
fsi_interface_test.vcd: fsi_master.v fsi_slave.v testbench_fsi.v
rm -f fsi_interface_sim
rm -f fsi_interface_test.vcd
/usr/bin/iverilog -DSIMULATION -o fsi_interface_sim fsi_master.v testbench_fsi.v
/usr/bin/iverilog -DSIMULATION -o fsi_interface_sim fsi_master.v fsi_slave.v testbench_fsi.v
./fsi_interface_sim
simulate_fsi: fsi_interface_test.vcd
......
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