Fix passage of received data from FSI master to higher logic levels

parent 7a6a81e7
......@@ -158,6 +158,7 @@ module fsi_master_interface(
always @(posedge peripheral_clock) begin
if (peripheral_reset) begin
cycle_complete_reg <= 0;
rx_data <= 0;
last_address_valid <= 0;
ipoll_in_process <= 0;
busy_response_in_process <= 0;
......@@ -719,6 +720,7 @@ module fsi_master_interface(
end else begin
// Transfer complete!
if (!ipoll_in_process) begin
rx_data <= rx_data_reg;
cycle_complete_reg <= 1;
end
busy_response_in_process <= 0;
......
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