Increase FSI TAR to 3 cycles for both master and slave

This is required due to the extra input register on both FSI master
and slave.  Without the extra turnaround time, stale data from the
TAR period can trigger spurious START signals.

As before, this value is not provided in the specification, but appears
to fall well below actual TAR times as observed on IBM POWER9 hardware.
parent cd63e8ce
......@@ -34,7 +34,7 @@ module fsi_master_interface(
);
parameter FSI_TIMEOUT_CYCLES = 256;
parameter FSI_TURNAROUND_CYCLES = 2;
parameter FSI_TURNAROUND_CYCLES = 3;
parameter FSI_MASTER_TIMEOUT_CYCLES = 166000; // Assumes 166MHz clock, 1ms timeout
parameter FSI_IPOLL_IDLE_START_CYCLES = 128; // This fires every ~786ns during idle periods if a 166MHz clock is used
parameter FSI_IPOLL_MAX_SEQ_STD_COMMANDS = 2; // Two commands can fire back-to-back without an IPOLL before an IPOLL is forcibly inserted
......
......@@ -33,7 +33,7 @@ module fsi_slave_interface(
// General FSI parameters
// NOTE: Must match standard / master parameters!
parameter FSI_TIMEOUT_CYCLES = 256;
parameter FSI_TURNAROUND_CYCLES = 2;
parameter FSI_TURNAROUND_CYCLES = 3;
// Slave specific parameters
parameter FSI_BUSY_TX_CYCLES = FSI_TIMEOUT_CYCLES-32; // Send BUSY messages 32 cycles before anticipated timeout
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment