Extend TAR cycle length to two clock cycles

This value is not provided in the specification, but appears to fall
well below actual TAR times as observed on IBM POWER9 hardware.

Extending to two clock cycles allows the bus to stabilize after
tristating has completed.
parent 62ae6bef
......@@ -31,7 +31,7 @@ module fsi_master_interface(
);
parameter FSI_TIMEOUT_CYCLES = 256;
parameter FSI_TURNAROUND_CYCLES = 1;
parameter FSI_TURNAROUND_CYCLES = 2;
parameter FSI_MASTER_TIMEOUT_CYCLES = 166000; // Assumes 166MHz clock, 1ms timeout
parameter FSI_IPOLL_IDLE_START_CYCLES = 128; // This fires every ~786ns during idle periods if a 166MHz clock is used
parameter FSI_IPOLL_MAX_SEQ_STD_COMMANDS = 2; // Two commands can fire back-to-back without an IPOLL before an IPOLL is forcibly inserted
......@@ -182,9 +182,11 @@ module fsi_master_interface(
crc_protected_bits_transmitting = 0;
crc_protected_bits_receiving = 0;
fsi_data_reg_internal = 1;
cycle_counter <= cycle_counter - 1;
if (cycle_counter == 1) begin
cycle_counter <= 0;
control_state <= FSI_INITIALIZE_STATE_03;
end else begin
cycle_counter <= cycle_counter - 1;
end
end else begin
// Should never reach this state
......@@ -195,12 +197,14 @@ module fsi_master_interface(
FSI_INITIALIZE_STATE_03: begin
// Transmission complete, switch direction
fsi_data_reg_internal = 0;
fsi_data_direction_reg <= 0;
if (cycle_counter >= (FSI_TURNAROUND_CYCLES - 1)) begin
timeout_counter <= 0;
ipoll_start_timer <= 0;
fsi_data_direction_reg <= 0;
control_state <= FSI_TRANSFER_STATE_IDLE;
end else begin
cycle_counter <= cycle_counter + 1;
end
end
FSI_TRANSFER_STATE_IDLE: begin
......@@ -447,13 +451,15 @@ module fsi_master_interface(
FSI_TRANSFER_STATE_TX10: begin
// Transmission complete, switch direction
fsi_data_reg_internal = 0;
fsi_data_direction_reg <= 0;
if (cycle_counter >= (FSI_TURNAROUND_CYCLES - 1)) begin
timeout_counter <= 0;
rx_data_reg <= 0;
crc_data <= 0;
fsi_data_direction_reg <= 0;
control_state <= FSI_TRANSFER_STATE_TX11;
end else begin
cycle_counter <= cycle_counter + 1;
end
end
FSI_TRANSFER_STATE_TX11: begin
......@@ -668,7 +674,6 @@ module fsi_master_interface(
FSI_TRANSFER_STATE_TR01: begin
// Reception complete, switch direction
fsi_data_reg_internal = 0;
fsi_data_direction_reg <= 0;
// Stop CRC generation
crc_protected_bits_transmitting = 0;
......@@ -739,6 +744,9 @@ module fsi_master_interface(
slave_error_recovery_state <= 0;
master_error_recovery_state <= 0;
end
fsi_data_direction_reg <= 0;
end else begin
cycle_counter <= cycle_counter + 1;
end
end
FSI_TRANSFER_STATE_TR02: begin
......
......@@ -33,7 +33,7 @@ module fsi_slave_interface(
// General FSI parameters
// NOTE: Must match standard / master parameters!
parameter FSI_TIMEOUT_CYCLES = 256;
parameter FSI_TURNAROUND_CYCLES = 1;
parameter FSI_TURNAROUND_CYCLES = 2;
// Slave specific parameters
parameter FSI_BUSY_TX_CYCLES = FSI_TIMEOUT_CYCLES-32; // Send BUSY messages 32 cycles before anticipated timeout
......@@ -484,7 +484,6 @@ module fsi_slave_interface(
FSI_TRANSFER_STATE_TR01: begin
// Reception complete, switch direction
fsi_data_reg_internal = 0;
fsi_data_direction_reg <= 0;
// Stop CRC generation
crc_protected_bits_transmitting = 0;
......@@ -512,6 +511,9 @@ module fsi_slave_interface(
busy_response_in_process <= 0;
control_state <= FSI_TRANSFER_STATE_TR02;
end
fsi_data_direction_reg <= 0;
end else begin
cycle_counter <= cycle_counter + 1;
end
end
FSI_TRANSFER_STATE_TR02: begin
......@@ -671,7 +673,6 @@ module fsi_slave_interface(
FSI_TRANSFER_STATE_TX07: begin
// Transmission complete, switch direction
fsi_data_reg_internal = 0;
fsi_data_direction_reg <= 0;
if (cycle_counter >= (FSI_TURNAROUND_CYCLES - 1)) begin
if (busy_response_in_process) begin
......@@ -686,6 +687,9 @@ module fsi_slave_interface(
crc_data <= 0;
control_state <= FSI_TRANSFER_STATE_IDLE;
end
fsi_data_direction_reg <= 0;
end else begin
cycle_counter <= cycle_counter + 1;
end
end
FSI_TRANSFER_STATE_IR01: begin
......
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