Move sequencer clock back to main LPC clock net

This avoids clock domain crossing glitches between the SPI
core and the sequencer logic.
parent 6dbeedb6
......@@ -116,14 +116,5 @@ module clock_generator(
assign slow_11hz_platform_clock = slow_clock_counter[20];
// Generate sequencer clock
reg sequencer_clock_internal = 0;
always @(posedge lpc_clock) begin
sequencer_clock_internal <= ~sequencer_clock_internal;
end
// Buffer sequencer clock
SB_GB platform_sequencer_clock_buffer (
.USER_SIGNAL_TO_GLOBAL_BUFFER(sequencer_clock_internal),
.GLOBAL_BUFFER_OUTPUT(sequencer_clock)
);
assign sequencer_clock = lpc_clock;
endmodule
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