- 17 Aug, 2017 6 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
This reverts commit b0470e94.
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 16 Aug, 2017 4 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 27 Jul, 2017 1 commit
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Sebastien Bourdeauducq authored
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- 11 Jul, 2017 1 commit
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Florent Kermarrec authored
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- 10 Jul, 2017 1 commit
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Florent Kermarrec authored
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- 08 Jul, 2017 2 commits
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whitequark authored
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mntng authored
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- 06 Jul, 2017 1 commit
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Robert Jordens authored
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- 04 Jul, 2017 2 commits
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Florent Kermarrec authored
This allows finer selection of signals when connection is partial.
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Florent Kermarrec authored
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- 02 Jul, 2017 2 commits
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Robert Jordens authored
* this is not a binary-to-gray encoder, i.e. no pipeline * binary and gray would otherwise be out-of-sync for one cycle, even and especially in the same clock domain * appears to be standard practice to ensure their synchronization (http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf) * causes problems in artiq
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Robert Jordens authored
data in pipelined registers is guaranteed to be clocked in from source signals at "full rate" and fully determined by those source registers. in that sense these registers don't hold intrinsic state that needs to be reset explicitly. their data can just flow in from the source (which is reset). having them reset_less delays their reset by one (or a few) clock cycles. if the target CD is reset, the data would just be reset for the duration of the target CD reset and then ("slowly") transition back to what the source CD has. control and handshaking logic needs to be reset.
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- 30 Jun, 2017 1 commit
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Robert Jordens authored
avoid the 2 ns delay rule erroneously catching any paths between two reset synchronizers (ff2 -> ff1).
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- 28 Jun, 2017 6 commits
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Florent Kermarrec authored
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
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- 25 Jun, 2017 4 commits
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Robert Jordens authored
* recommended as per https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug894-vivado-tcl-scripting.pdf * does not appear to be too expensive but beneficial to do here
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Robert Jordens authored
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Robert Jordens authored
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Lukas Lao Beyer authored
There's a 'width' attribute -- so why no 'depth', too?
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- 21 Jun, 2017 1 commit
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Robert Jordens authored
* drop ars_meta as vavado seems to forget it sometimes * mark the metastable path via the cells * .. and the input via the net and the cells
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- 18 Jun, 2017 8 commits
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Robert Jordens authored
Support for reset-less Signals avoids having to create a reset_less clock domain just to be able to have a single reset_less register. This is helpful when inferring primitives that do not support resets, e.g. SRL* shift registers in spartan 6. As an important sideeffect, the synchronous reset logic has been rewritten from if (rst) <rst> else <code> end to <code> if (rst) <rst>
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Robert Jordens authored
* asr-false-path: vivado: create ars_meta, ars_false_path properties verilog: add space before instance attrs fhdl: add attr to Instances vivado/AsyncResetSync: use asr_async_reg property vivado: (fix) copy async reg to driving cells vivado/AsyncResetSync: only wrap async_reset input when necessary vivado: fix abbreviation vivado: copy async_reg from wires to cell inputs vivado/AsyncResetSync: constrain metastable path, fix false_path vivado: save project xilinx: false_path the first register in AsyncResetSynchronizer vivado: create project explicitly
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
* and use it for async_reg in XilinxAsyncResetSynchronizerImpl
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Robert Jordens authored
* do not collide with the original working async_reg property on regs or wires inferred off of regs
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Robert Jordens authored
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Robert Jordens authored
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