1. 17 Aug, 2017 6 commits
  2. 16 Aug, 2017 4 commits
  3. 27 Jul, 2017 1 commit
  4. 11 Jul, 2017 1 commit
  5. 10 Jul, 2017 1 commit
  6. 08 Jul, 2017 2 commits
  7. 06 Jul, 2017 1 commit
  8. 04 Jul, 2017 2 commits
  9. 02 Jul, 2017 2 commits
    • Robert Jordens's avatar
      cdc: reset GrayCounter gray output early · ee0e7091
      Robert Jordens authored
      * this is not a binary-to-gray encoder, i.e. no pipeline
      * binary and gray would otherwise be out-of-sync for one cycle, even and
      especially in the same clock domain
      * appears to be standard practice to ensure their synchronization
      (http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf)
      * causes problems in artiq
      ee0e7091
    • Robert Jordens's avatar
      cdc: make pipelined registers reset_less · 3e72a835
      Robert Jordens authored
      data in pipelined registers is guaranteed to be clocked in from source
      signals at "full rate" and fully determined by those source registers.
      in that sense these registers don't hold intrinsic state that needs to
      be reset explicitly. their data can just flow in from the source (which
      is reset).
      having them reset_less delays their reset by one (or a few) clock cycles.
      if the target CD is reset, the data would just be reset for the duration
      of the target CD reset and then ("slowly") transition back to what the
      source CD has.
      control and handshaking logic needs to be reset.
      3e72a835
  10. 30 Jun, 2017 1 commit
  11. 28 Jun, 2017 6 commits
  12. 25 Jun, 2017 4 commits
  13. 21 Jun, 2017 1 commit
  14. 18 Jun, 2017 8 commits