Commit feece924 authored by Robert Jordens's avatar Robert Jordens
Browse files

vivado: strictify AsyncResetSynchronizer constraints

* drop ars_meta as vavado seems to forget it sometimes
* mark the metastable path via the cells
* .. and the input via the net and the cells
parent c1da39d4
......@@ -82,12 +82,13 @@ class XilinxAsyncResetSynchronizerImpl(Module):
rst_meta = Signal()
self.specials += [
Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
i_CE=1, i_C=cd.clk, o_Q=rst_meta, attr={"async_reg"}),
i_CE=1, i_C=cd.clk, o_Q=rst_meta,
attr={"async_reg", "ars_ff"}),
Instance("FDPE", p_INIT=1, i_D=rst_meta, i_PRE=async_reset,
i_CE=1, i_C=cd.clk, o_Q=cd.rst, attr={"async_reg"})
i_CE=1, i_C=cd.clk, o_Q=cd.rst,
attr={"async_reg", "ars_ff"})
]
async_reset.attr.add("ars_false_path")
rst_meta.attr.add("ars_meta")
class XilinxAsyncResetSynchronizer:
......
......@@ -129,7 +129,7 @@ class XilinxISEToolchain:
"keep": ("keep", "true"),
"no_retiming": ("register_balancing", "no"),
"async_reg": None,
"ars_false_path": None,
"ars_ff": None,
"ars_meta": None,
"no_shreg_extract": ("shreg_extract", "no")
}
......
......@@ -75,7 +75,7 @@ class XilinxVivadoToolchain:
"keep": ("dont_touch", "true"),
"no_retiming": ("dont_touch", "true"),
"async_reg": ("async_reg", "true"),
"ars_meta": ("ars_meta", "true"), # user-defined attribute
"ars_ff": ("ars_ff", "true"), # user-defined attribute
"ars_false_path": ("ars_false_path", "true"), # user-defined attribute
"no_shreg_extract": None
}
......@@ -92,7 +92,7 @@ class XilinxVivadoToolchain:
tcl = []
tcl.append("create_project -force -part {} {}".format(
platform.device, build_name))
tcl.append("create_property ars_meta net")
tcl.append("create_property ars_ff cell")
tcl.append("create_property ars_false_path net")
for filename, language, library in sources:
filename_tcl = "{" + filename + "}"
......@@ -153,14 +153,16 @@ class XilinxVivadoToolchain:
# The asychronous reset input to the AsyncResetSynchronizer is a false
# path
platform.add_platform_command(
"set_false_path -quiet -through "
"[get_nets -hier -filter {{ars_false_path==true}}]"
"set_false_path -quiet "
"-through [get_nets -hier -filter {{ars_false_path==true}}] "
"-to [get_cells -hier -filter {{ars_ff==true}}]"
)
# clock_period-2ns to resolve metastability on the wire between the
# AsyncResetSynchronizer FFs
platform.add_platform_command(
"set_max_delay 2 -quiet -through "
"[get_nets -hier -filter {{ars_meta==true}}]"
"set_max_delay 2 -quiet "
"-from [get_cells -hier -filter {{ars_ff==true}}] "
"-to [get_cells -hier -filter {{ars_ff==true}}]"
)
def build(self, platform, fragment, build_dir="build", build_name="top",
......
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