support reset-less Signals (closes #54)
Support for reset-less Signals avoids having to create a reset_less clock domain just to be able to have a single reset_less register. This is helpful when inferring primitives that do not support resets, e.g. SRL* shift registers in spartan 6. As an important sideeffect, the synchronous reset logic has been rewritten from if (rst) <rst> else <code> end to <code> if (rst) <rst>
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