Merge branch 'asr-false-path'
* asr-false-path: vivado: create ars_meta, ars_false_path properties verilog: add space before instance attrs fhdl: add attr to Instances vivado/AsyncResetSync: use asr_async_reg property vivado: (fix) copy async reg to driving cells vivado/AsyncResetSync: only wrap async_reset input when necessary vivado: fix abbreviation vivado: copy async_reg from wires to cell inputs vivado/AsyncResetSync: constrain metastable path, fix false_path vivado: save project xilinx: false_path the first register in AsyncResetSynchronizer vivado: create project explicitly
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