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Kestrel Collaboration
Kestrel LiteX
migen
Commits
d8860cde
Commit
d8860cde
authored
7 years ago
by
Sebastien Bourdeauducq
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xilinx: add 7-series DDR input
parent
6169265e
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+17
-1
migen/build/xilinx/common.py
migen/build/xilinx/common.py
+17
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migen/build/xilinx/common.py
View file @
d8860cde
...
...
@@ -162,8 +162,24 @@ class XilinxDDROutputS7:
return
XilinxDDROutputImplS7
(
dr
.
i1
,
dr
.
i2
,
dr
.
o
,
dr
.
clk
)
class
XilinxDDRInputImplS7
(
Module
):
def
__init__
(
self
,
i
,
o1
,
o2
,
clk
):
self
.
specials
+=
Instance
(
"IDDR"
,
p_DDR_CLK_EDGE
=
"SAME_EDGE_PIPELINED"
,
i_C
=
clk
,
i_CE
=
1
,
i_S
=
0
,
i_R
=
0
,
o_D
=
i
,
i_Q1
=
o1
,
i_Q2
=
o2
,
)
class
XilinxDDRInputS7
:
@
staticmethod
def
lower
(
dr
):
return
XilinxDDRInputImplS7
(
dr
.
i
,
dr
.
o1
,
dr
.
o2
,
dr
.
clk
)
xilinx_s7_special_overrides
=
{
DDROutput
:
XilinxDDROutputS7
DDROutput
:
XilinxDDROutputS7
,
DDRInput
:
XilinxDDRInputS7
}
...
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