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Kestrel Collaboration
Kestrel LiteX
migen
Commits
6169265e
Commit
6169265e
authored
7 years ago
by
Sebastien Bourdeauducq
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xilinx: move Spartan-6 DDR output out of generic Xilinx special overrides
parent
970428e0
Changes
2
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2 changed files
with
15 additions
and
9 deletions
+15
-9
migen/build/xilinx/common.py
migen/build/xilinx/common.py
+13
-9
migen/build/xilinx/platform.py
migen/build/xilinx/platform.py
+2
-0
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migen/build/xilinx/common.py
View file @
6169265e
...
@@ -119,7 +119,15 @@ class XilinxDifferentialOutput:
...
@@ -119,7 +119,15 @@ class XilinxDifferentialOutput:
return
XilinxDifferentialOutputImpl
(
dr
.
i
,
dr
.
o_p
,
dr
.
o_n
)
return
XilinxDifferentialOutputImpl
(
dr
.
i
,
dr
.
o_p
,
dr
.
o_n
)
class
XilinxDDROutputImpl
(
Module
):
xilinx_special_overrides
=
{
MultiReg
:
XilinxMultiReg
,
AsyncResetSynchronizer
:
XilinxAsyncResetSynchronizer
,
DifferentialInput
:
XilinxDifferentialInput
,
DifferentialOutput
:
XilinxDifferentialOutput
}
class
XilinxDDROutputImplS6
(
Module
):
def
__init__
(
self
,
i1
,
i2
,
o
,
clk
):
def
__init__
(
self
,
i1
,
i2
,
o
,
clk
):
self
.
specials
+=
Instance
(
"ODDR2"
,
self
.
specials
+=
Instance
(
"ODDR2"
,
p_DDR_ALIGNMENT
=
"NONE"
,
p_INIT
=
0
,
p_SRTYPE
=
"SYNC"
,
p_DDR_ALIGNMENT
=
"NONE"
,
p_INIT
=
0
,
p_SRTYPE
=
"SYNC"
,
...
@@ -128,18 +136,14 @@ class XilinxDDROutputImpl(Module):
...
@@ -128,18 +136,14 @@ class XilinxDDROutputImpl(Module):
)
)
class
XilinxDDROutput
:
class
XilinxDDROutput
S6
:
@
staticmethod
@
staticmethod
def
lower
(
dr
):
def
lower
(
dr
):
return
XilinxDDROutputImpl
(
dr
.
i1
,
dr
.
i2
,
dr
.
o
,
dr
.
clk
)
return
XilinxDDROutputImpl
S6
(
dr
.
i1
,
dr
.
i2
,
dr
.
o
,
dr
.
clk
)
xilinx_special_overrides
=
{
xilinx_s6_special_overrides
=
{
MultiReg
:
XilinxMultiReg
,
DDROutput
:
XilinxDDROutputS6
AsyncResetSynchronizer
:
XilinxAsyncResetSynchronizer
,
DifferentialInput
:
XilinxDifferentialInput
,
DifferentialOutput
:
XilinxDifferentialOutput
,
DDROutput
:
XilinxDDROutput
}
}
...
...
This diff is collapsed.
Click to expand it.
migen/build/xilinx/platform.py
View file @
6169265e
...
@@ -16,6 +16,8 @@ class XilinxPlatform(GenericPlatform):
...
@@ -16,6 +16,8 @@ class XilinxPlatform(GenericPlatform):
def
get_verilog
(
self
,
*
args
,
special_overrides
=
dict
(),
**
kwargs
):
def
get_verilog
(
self
,
*
args
,
special_overrides
=
dict
(),
**
kwargs
):
so
=
dict
(
common
.
xilinx_special_overrides
)
so
=
dict
(
common
.
xilinx_special_overrides
)
if
self
.
device
[:
3
]
==
"xc6"
:
so
.
update
(
common
.
xilinx_s6_special_overrides
)
if
self
.
device
[:
3
]
==
"xc7"
:
if
self
.
device
[:
3
]
==
"xc7"
:
so
.
update
(
common
.
xilinx_s7_special_overrides
)
so
.
update
(
common
.
xilinx_s7_special_overrides
)
if
self
.
device
[:
4
]
==
"xcku"
:
if
self
.
device
[:
4
]
==
"xcku"
:
...
...
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Click to expand it.
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