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Kestrel Collaboration
Kestrel LiteX
migen
Commits
959f9cbc
Commit
959f9cbc
authored
7 years ago
by
Robert Jordens
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vivado/AsyncResetSync: only wrap async_reset input when necessary
parent
fe7d5bf1
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1
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with
7 additions
and
8 deletions
+7
-8
migen/build/xilinx/common.py
migen/build/xilinx/common.py
+7
-8
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migen/build/xilinx/common.py
View file @
959f9cbc
...
...
@@ -75,19 +75,18 @@ class XilinxMultiReg:
class
XilinxAsyncResetSynchronizerImpl
(
Module
):
def
__init__
(
self
,
cd
,
reset_in
):
rst_async
=
Signal
()
def
__init__
(
self
,
cd
,
async_reset
):
if
not
hasattr
(
async_reset
,
"attr"
):
i
,
async_reset
=
async_reset
,
Signal
()
self
.
comb
+=
async_reset
.
eq
(
i
)
rst_meta
=
Signal
()
self
.
specials
+=
[
Instance
(
"FDPE"
,
p_INIT
=
1
,
i_D
=
0
,
i_PRE
=
rst_
async
,
Instance
(
"FDPE"
,
p_INIT
=
1
,
i_D
=
0
,
i_PRE
=
async
_reset
,
i_CE
=
1
,
i_C
=
cd
.
clk
,
o_Q
=
rst_meta
),
Instance
(
"FDPE"
,
p_INIT
=
1
,
i_D
=
rst_meta
,
i_PRE
=
rst_
async
,
Instance
(
"FDPE"
,
p_INIT
=
1
,
i_D
=
rst_meta
,
i_PRE
=
async
_reset
,
i_CE
=
1
,
i_C
=
cd
.
clk
,
o_Q
=
cd
.
rst
)
]
self
.
comb
+=
[
rst_async
.
eq
(
reset_in
)
]
rst_async
.
attr
.
add
(
"ars_false_path"
)
async_reset
.
attr
.
add
(
"ars_false_path"
)
rst_meta
.
attr
.
add
(
"ars_meta"
)
rst_meta
.
attr
.
add
(
"async_reg"
)
cd
.
rst
.
attr
.
add
(
"async_reg"
)
...
...
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