Commit c2ea27d5 authored by Robert Jordens's avatar Robert Jordens
Browse files

vivado: (fix) copy async reg to driving cells

parent 959f9cbc
......@@ -160,11 +160,11 @@ class XilinxVivadoToolchain:
"set_max_delay 2 -quiet -through "
"[get_nets -hier -filter {{ars_meta==true}}]"
)
# copy async_reg from wires to cell inputs
# copy async_reg from wires to driving cells
platform.add_platform_command(
"set_property -quiet ASYNC_REG 1 [get_cells -of [get_pins -of "
"[get_nets -hier -filter {{async_reg==true}}] -filter "
"{{DIRECTION==IN}}]]"
"{{DIRECTION==OUT}}]]"
)
def build(self, platform, fragment, build_dir="build", build_name="top",
......
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