Commit 7cee63d7 authored by Robert Jordens's avatar Robert Jordens
Browse files

vivado/AsyncResetSync: use asr_async_reg property

* do not collide with the original working async_reg property
on regs or wires inferred off of regs
parent c2ea27d5
......@@ -88,8 +88,8 @@ class XilinxAsyncResetSynchronizerImpl(Module):
]
async_reset.attr.add("ars_false_path")
rst_meta.attr.add("ars_meta")
rst_meta.attr.add("async_reg")
cd.rst.attr.add("async_reg")
rst_meta.attr.add("ars_async_reg")
cd.rst.attr.add("ars_async_reg")
class XilinxAsyncResetSynchronizer:
......
......@@ -131,6 +131,7 @@ class XilinxISEToolchain:
"async_reg": None,
"ars_false_path": None,
"ars_meta": None,
"ars_async_reg": None,
"no_shreg_extract": ("shreg_extract", "no")
}
......
......@@ -77,6 +77,7 @@ class XilinxVivadoToolchain:
"async_reg": ("async_reg", "true"),
"ars_meta": ("ars_meta", "true"), # user-defined attribute
"ars_false_path": ("ars_false_path", "true"), # user-defined attribute
"ars_async_reg": ("ars_async_reg", "true"), # user-defined attribute
"no_shreg_extract": None
}
......@@ -163,7 +164,7 @@ class XilinxVivadoToolchain:
# copy async_reg from wires to driving cells
platform.add_platform_command(
"set_property -quiet ASYNC_REG 1 [get_cells -of [get_pins -of "
"[get_nets -hier -filter {{async_reg==true}}] -filter "
"[get_nets -hier -filter {{ars_async_reg==true}}] -filter "
"{{DIRECTION==OUT}}]]"
)
......
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