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Kestrel Collaboration
Kestrel LiteX
migen
Commits
f7816e4a
Commit
f7816e4a
authored
7 years ago
by
Sebastien Bourdeauducq
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sayma_amc: add Ethernet clock constraints
parent
ae063b2f
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migen/build/platforms/sinara/sayma_amc.py
migen/build/platforms/sinara/sayma_amc.py
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migen/build/platforms/sinara/sayma_amc.py
View file @
f7816e4a
...
...
@@ -111,3 +111,14 @@ class Platform(XilinxPlatform):
def
__init__
(
self
):
XilinxPlatform
.
__init__
(
self
,
"xcku040-ffva1156-1-c"
,
_io
,
toolchain
=
"vivado"
)
def
do_finalize
(
self
,
fragment
):
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
).
rx
,
8.0
)
except
ConstraintError
:
pass
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
).
tx
,
8.0
)
except
ConstraintError
:
pass
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