Commit f7816e4a authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
Browse files

sayma_amc: add Ethernet clock constraints

parent ae063b2f
......@@ -111,3 +111,14 @@ class Platform(XilinxPlatform):
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-1-c", _io, toolchain="vivado")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").tx, 8.0)
except ConstraintError:
pass
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