- 18 Jun, 2017 12 commits
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Robert Jordens authored
Support for reset-less Signals avoids having to create a reset_less clock domain just to be able to have a single reset_less register. This is helpful when inferring primitives that do not support resets, e.g. SRL* shift registers in spartan 6. As an important sideeffect, the synchronous reset logic has been rewritten from if (rst) <rst> else <code> end to <code> if (rst) <rst>
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Robert Jordens authored
* asr-false-path: vivado: create ars_meta, ars_false_path properties verilog: add space before instance attrs fhdl: add attr to Instances vivado/AsyncResetSync: use asr_async_reg property vivado: (fix) copy async reg to driving cells vivado/AsyncResetSync: only wrap async_reset input when necessary vivado: fix abbreviation vivado: copy async_reg from wires to cell inputs vivado/AsyncResetSync: constrain metastable path, fix false_path vivado: save project xilinx: false_path the first register in AsyncResetSynchronizer vivado: create project explicitly
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
* and use it for async_reg in XilinxAsyncResetSynchronizerImpl
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Robert Jordens authored
* do not collide with the original working async_reg property on regs or wires inferred off of regs
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
ASYNC_REG can only be applied to cells https://www.xilinx.com/support/answers/64019.html
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Robert Jordens authored
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Robert Jordens authored
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- 17 Jun, 2017 2 commits
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Robert Jordens authored
- 31 May, 2017 2 commits
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Florent Kermarrec authored
latency can't be reduced that much and reducing ressource usage (already low) would introduce unneeded complexity.
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Florent Kermarrec authored
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- 27 May, 2017 1 commit
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whitequark authored
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- 26 May, 2017 2 commits
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whitequark authored
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whitequark authored
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- 08 May, 2017 1 commit
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Robert Jordens authored
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- 25 Apr, 2017 6 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
ultrascale ISERDESE3 do not have integrated bitslip so we need one and that's probably better since Xilinx bitslip implementation is always obscure... We could also use it for Kintex7 and Spartan6 ddr phys.
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Florent Kermarrec authored
build/lattice/programmer: provide xcf_template on init (template is not generic enough to be in migen)
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 12 Apr, 2017 1 commit
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Rohit Kumar Singh authored
Fixes #66 issue which resulted in creation of redundant clock domains
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- 01 Apr, 2017 1 commit
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Sebastien Bourdeauducq authored
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- 27 Mar, 2017 8 commits
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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- 11 Mar, 2017 3 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 20 Feb, 2017 1 commit
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Sebastien Bourdeauducq authored
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