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Kestrel Collaboration
Kestrel LiteX
migen
Commits
070baf8b
Commit
070baf8b
authored
7 years ago
by
Robert Jordens
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vivado/AsyncResetSync: constrain metastable path, fix false_path
parent
1a5cdd57
Changes
3
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3 changed files
with
24 additions
and
9 deletions
+24
-9
migen/build/xilinx/common.py
migen/build/xilinx/common.py
+12
-7
migen/build/xilinx/ise.py
migen/build/xilinx/ise.py
+1
-0
migen/build/xilinx/vivado.py
migen/build/xilinx/vivado.py
+11
-2
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migen/build/xilinx/common.py
View file @
070baf8b
...
...
@@ -75,16 +75,21 @@ class XilinxMultiReg:
class
XilinxAsyncResetSynchronizerImpl
(
Module
):
def
__init__
(
self
,
cd
,
async_reset
):
rst1
=
Signal
()
def
__init__
(
self
,
cd
,
reset_in
):
rst_async
=
Signal
()
rst_meta
=
Signal
()
self
.
specials
+=
[
Instance
(
"FDPE"
,
p_INIT
=
1
,
i_D
=
0
,
i_PRE
=
async
_reset
,
i_CE
=
1
,
i_C
=
cd
.
clk
,
o_Q
=
rst
1
),
Instance
(
"FDPE"
,
p_INIT
=
1
,
i_D
=
rst
1
,
i_PRE
=
async
_reset
,
Instance
(
"FDPE"
,
p_INIT
=
1
,
i_D
=
0
,
i_PRE
=
rst_
async
,
i_CE
=
1
,
i_C
=
cd
.
clk
,
o_Q
=
rst
_meta
),
Instance
(
"FDPE"
,
p_INIT
=
1
,
i_D
=
rst
_meta
,
i_PRE
=
rst_
async
,
i_CE
=
1
,
i_C
=
cd
.
clk
,
o_Q
=
cd
.
rst
)
]
rst1
.
attr
.
add
(
"asr_false_path"
)
rst1
.
attr
.
add
(
"async_reg"
)
self
.
comb
+=
[
rst_async
.
eq
(
reset_in
)
]
rst_async
.
attr
.
add
(
"asr_false_path"
)
rst_meta
.
attr
.
add
(
"asr_meta"
)
rst_meta
.
attr
.
add
(
"async_reg"
)
cd
.
rst
.
attr
.
add
(
"async_reg"
)
...
...
This diff is collapsed.
Click to expand it.
migen/build/xilinx/ise.py
View file @
070baf8b
...
...
@@ -130,6 +130,7 @@ class XilinxISEToolchain:
"no_retiming"
:
(
"register_balancing"
,
"no"
),
"async_reg"
:
None
,
"asr_false_path"
:
None
,
"asr_meta"
:
None
,
"no_shreg_extract"
:
(
"shreg_extract"
,
"no"
)
}
...
...
This diff is collapsed.
Click to expand it.
migen/build/xilinx/vivado.py
View file @
070baf8b
...
...
@@ -75,6 +75,7 @@ class XilinxVivadoToolchain:
"keep"
:
(
"dont_touch"
,
"true"
),
"no_retiming"
:
(
"dont_touch"
,
"true"
),
"async_reg"
:
(
"async_reg"
,
"true"
),
"asr_meta"
:
(
"asr_meta"
,
"true"
),
# user-defined attribute
"asr_false_path"
:
(
"asr_false_path"
,
"true"
),
# user-defined attribute
"no_shreg_extract"
:
None
}
...
...
@@ -147,9 +148,17 @@ class XilinxVivadoToolchain:
del
self
.
false_paths
def
_constrain
(
self
,
platform
):
# The asychronous reset input to the AsyncResetSynchronizer is a false
# path
platform
.
add_platform_command
(
"set_false_path -to [get_cells -of_objects "
"[get_nets -hier -filter {{asr_false_path==true}}]]"
"set_false_path -quiet -through "
"[get_nets -hier -filter {{asr_false_path==true}}]"
)
# clock_period-2ns to resolve metastability on the wire between the
# AsyncResetSynchronizer FFs
platform
.
add_platform_command
(
"set_max_delay 2 -quiet -through "
"[get_nets -hier -filter {{asr_meta==true}}]"
)
def
build
(
self
,
platform
,
fragment
,
build_dir
=
"build"
,
build_name
=
"top"
,
...
...
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