Commit 78b056ab authored by Florent Kermarrec's avatar Florent Kermarrec
Browse files

genlib/misc: add BitSlip

ultrascale ISERDESE3 do not have integrated bitslip so we need one and that's probably better since Xilinx bitslip implementation is always obscure...
We could also use it for Kintex7 and Spartan6 ddr phys.
parent 66b20303
...@@ -86,3 +86,19 @@ class WaitTimer(Module): ...@@ -86,3 +86,19 @@ class WaitTimer(Module):
If(self.wait, If(self.wait,
If(~self.done, count.eq(count - 1)) If(~self.done, count.eq(count - 1))
).Else(count.eq(count.reset)) ).Else(count.eq(count.reset))
class BitSlip(Module):
def __init__(self, dw):
self.i = Signal(dw)
self.o = Signal(dw)
self.value = Signal(max=dw)
# # #
r = Signal(2*dw)
self.sync += r.eq(Cat(r[dw:], self.i))
cases = {}
for i in range(dw):
cases[i] = self.o.eq(r[i:dw+i])
self.sync += Case(self.value, cases)
import unittest
import random
from migen import *
from migen.genlib.misc import BitSlip
class BitSlipModel:
def __init__(self, data_width, latency):
self.data_width = data_width
self.latency = latency
def simulate(self, bitslip, sequence):
# prepare sequence for simulation
s = [0]*self.latency
for d in sequence:
s.append(d)
# simulate bitslip
r = []
for i in range(len(s)-1):
v = (s[i+1] << self.data_width) | s[i]
v = v >> bitslip
v &= 2**self.data_width-1
r.append(v)
return r
def main_generator(dut):
dut.o_sequence = []
yield dut.value.eq(dut.bitslip)
for i, data in enumerate(dut.i_sequence):
yield dut.i.eq(data)
dut.o_sequence.append((yield dut.o))
yield
class TestBitSlip(unittest.TestCase):
def bitslip_test(self, data_width, length=128):
prng = random.Random(42)
sequence = [prng.randrange(2**data_width) for i in range(length)]
for i in range(data_width):
dut = BitSlip(data_width)
dut.bitslip = i
dut.i_sequence = sequence
run_simulation(dut, main_generator(dut))
model = BitSlipModel(data_width, 4)
m_sequence = model.simulate(i, sequence)
self.assertEqual(dut.o_sequence, m_sequence[:len(dut.o_sequence)])
def test_bitslip_4b(self):
self.bitslip_test(4)
def test_bitslip_8b(self):
self.bitslip_test(8)
def test_bitslip_16b(self):
self.bitslip_test(16)
def test_bitslip_32b(self):
self.bitslip_test(32)
def test_bitslip_64b(self):
self.bitslip_test(64)
def test_bitslip_128b(self):
self.bitslip_test(128)
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