- 30 Aug, 2017 1 commit
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Sebastien Bourdeauducq authored
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- 26 Aug, 2017 3 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 21 Aug, 2017 4 commits
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Robert Jordens authored
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Robert Jordens authored
From 114590496cd9e609a162d73a0b5c404f8e07a5906607d486f86790d1463e1381 /tmp/Sayma_AMC_platform.xdc
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 20 Aug, 2017 7 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 17 Aug, 2017 6 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
This reverts commit b0470e94.
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 16 Aug, 2017 4 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 27 Jul, 2017 1 commit
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Sebastien Bourdeauducq authored
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- 11 Jul, 2017 1 commit
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Florent Kermarrec authored
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- 10 Jul, 2017 1 commit
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Florent Kermarrec authored
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- 08 Jul, 2017 2 commits
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whitequark authored
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mntng authored
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- 06 Jul, 2017 1 commit
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Robert Jordens authored
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- 04 Jul, 2017 2 commits
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Florent Kermarrec authored
This allows finer selection of signals when connection is partial.
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Florent Kermarrec authored
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- 02 Jul, 2017 2 commits
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Robert Jordens authored
* this is not a binary-to-gray encoder, i.e. no pipeline * binary and gray would otherwise be out-of-sync for one cycle, even and especially in the same clock domain * appears to be standard practice to ensure their synchronization (http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf) * causes problems in artiq
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Robert Jordens authored
data in pipelined registers is guaranteed to be clocked in from source signals at "full rate" and fully determined by those source registers. in that sense these registers don't hold intrinsic state that needs to be reset explicitly. their data can just flow in from the source (which is reset). having them reset_less delays their reset by one (or a few) clock cycles. if the target CD is reset, the data would just be reset for the duration of the target CD reset and then ("slowly") transition back to what the source CD has. control and handshaking logic needs to be reset.
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- 30 Jun, 2017 1 commit
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Robert Jordens authored
avoid the 2 ns delay rule erroneously catching any paths between two reset synchronizers (ff2 -> ff1).
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- 28 Jun, 2017 4 commits
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Florent Kermarrec authored
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
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