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Kestrel Collaboration
Kestrel LiteX
migen
Commits
0f78f9f7
Commit
0f78f9f7
authored
7 years ago
by
Sebastien Bourdeauducq
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sayma_amc: fix FTDI UART I/O voltage
parent
26da3498
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1
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migen/build/platforms/sinara/sayma_amc.py
migen/build/platforms/sinara/sayma_amc.py
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migen/build/platforms/sinara/sayma_amc.py
View file @
0f78f9f7
...
...
@@ -13,12 +13,12 @@ _io = [
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"AK8"
)),
Subsignal
(
"rx"
,
Pins
(
"AL8"
)),
IOStandard
(
"LVCMOS
18
"
)
IOStandard
(
"LVCMOS
33
"
)
),
(
"serial"
,
1
,
Subsignal
(
"tx"
,
Pins
(
"M27"
)),
Subsignal
(
"rx"
,
Pins
(
"L27"
)),
IOStandard
(
"LVCMOS
18
"
)
IOStandard
(
"LVCMOS
33
"
)
),
(
"serial_rtm"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"G27"
)),
...
...
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