- 18 Jun, 2017 6 commits
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
ASYNC_REG can only be applied to cells https://www.xilinx.com/support/answers/64019.html
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Robert Jordens authored
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Robert Jordens authored
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- 17 Jun, 2017 2 commits
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Robert Jordens authored
- 31 May, 2017 2 commits
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Florent Kermarrec authored
latency can't be reduced that much and reducing ressource usage (already low) would introduce unneeded complexity.
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Florent Kermarrec authored
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- 27 May, 2017 1 commit
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whitequark authored
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- 26 May, 2017 2 commits
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whitequark authored
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whitequark authored
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- 08 May, 2017 1 commit
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Robert Jordens authored
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- 25 Apr, 2017 6 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
ultrascale ISERDESE3 do not have integrated bitslip so we need one and that's probably better since Xilinx bitslip implementation is always obscure... We could also use it for Kintex7 and Spartan6 ddr phys.
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Florent Kermarrec authored
build/lattice/programmer: provide xcf_template on init (template is not generic enough to be in migen)
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 12 Apr, 2017 1 commit
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Rohit Kumar Singh authored
Fixes #66 issue which resulted in creation of redundant clock domains
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- 01 Apr, 2017 1 commit
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Sebastien Bourdeauducq authored
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- 27 Mar, 2017 8 commits
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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Tim 'mithro' Ansell authored
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- 11 Mar, 2017 3 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 20 Feb, 2017 2 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 10 Feb, 2017 1 commit
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whitequark authored
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- 27 Jan, 2017 1 commit
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Robert Jordens authored
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- 25 Jan, 2017 2 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 18 Dec, 2016 1 commit
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Elvira Khabirova authored
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