- 25 Feb, 2019 2 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 19 Feb, 2019 1 commit
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Sean Cross authored
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- 31 Jan, 2019 1 commit
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Sebastien Bourdeauducq authored
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- 30 Jan, 2019 1 commit
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msloniewski authored
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- 25 Jan, 2019 1 commit
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Sebastien Bourdeauducq authored
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- 16 Jan, 2019 1 commit
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Sebastien Bourdeauducq authored
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- 15 Jan, 2019 1 commit
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AlexanderKnapik authored
The eth_reset_n and eth_int_n pins were set to the same value of B14. I'm updating the pin of eth_reset_n to B4 as on the schematic.
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- 07 Jan, 2019 1 commit
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Sebastien Bourdeauducq authored
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- 06 Jan, 2019 1 commit
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Sebastien Bourdeauducq authored
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- 05 Jan, 2019 2 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 02 Jan, 2019 1 commit
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Sebastien Bourdeauducq authored
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- 31 Dec, 2018 1 commit
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William D. Jones authored
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- 29 Dec, 2018 1 commit
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Christian Vogel authored
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- 22 Dec, 2018 1 commit
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Florent Kermarrec authored
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- 16 Dec, 2018 1 commit
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Tim 'mithro' Ansell authored
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- 12 Dec, 2018 1 commit
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Pierre-Olivier Vauboin authored
Add support for new opcode CALL_METHOD https://docs.python.org/3/library/dis.html#opcode-CALL_METHOD
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- 09 Dec, 2018 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
In some simulation cases, it's easier to add debug traces directly in the code than in the verilog/Migen testbench. This adds support for verilog $display in Migen code. Being able to terminate a simulation from the code is also useful, this also add support for verilog $finish.
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- 05 Dec, 2018 1 commit
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whitequark authored
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- 04 Dec, 2018 2 commits
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whitequark authored
This reverts commit 2dc085d7. The case of nbits==1 when used with a multi-bit toplevel port results in generated Verilog similar to: module top( inout [7:0] io, ); SB_IO #( .PIN_TYPE(6'd41) ) SB_IO_21 ( .D_OUT_0(t_o), .OUTPUT_ENABLE(t_oe), .PACKAGE_PIN(io[0][0]), .D_IN_0(t_i) ); endmodule This is not legal as it is not permitted to index into a 1-bit signal.
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whitequark authored
This makes distinct memories have different names in gtkwave.
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- 01 Dec, 2018 2 commits
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whitequark authored
The conditions in them were different: _can_lower() checked for presence of the lower() override method, and _lower_specials_step() would only lower the special if lower() is present and returns something other than None. Remove _can_lower() and instead lower specials until no more can be lowered. This is also both simpler and faster.
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whitequark authored
This allows using values such as ClockSignal() and ResetSignal() in specials. Also, this commit removes a mismatch between simulation and Verilog synthesis in the way they were using lower_specials().
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- 27 Nov, 2018 2 commits
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whitequark authored
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whitequark authored
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- 25 Nov, 2018 4 commits
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whitequark authored
Only works in nextpnr, of course.
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whitequark authored
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whitequark authored
This makes for significantly more legible PNR reports in cases where TSTriples are being generated automatically, like in Glasgow.
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whitequark authored
Also, write .svf file directly alongside .bit file.
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- 24 Nov, 2018 1 commit
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Adam Greig authored
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- 20 Nov, 2018 1 commit
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William D. Jones authored
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- 17 Nov, 2018 1 commit
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- 13 Nov, 2018 3 commits
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whitequark authored
This is be useful for writing "generalized FSMs", for example: * an FSM that is expanded at build time into a pipeline, to switch through more than one state per cycle; * an FSM specialized for making parsers that work over an arbitrary datapath width.
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whitequark authored
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whitequark authored
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- 12 Nov, 2018 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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