Commit 5e7c71ac authored by Florent Kermarrec's avatar Florent Kermarrec
Browse files

build/xilinx/vivado: use build_name instead of top in synth_design

parent 37db6bb5
...@@ -116,9 +116,9 @@ class XilinxVivadoToolchain: ...@@ -116,9 +116,9 @@ class XilinxVivadoToolchain:
tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands) tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
# "-include_dirs {}" crashes Vivado 2016.4 # "-include_dirs {}" crashes Vivado 2016.4
if platform.verilog_include_paths: if platform.verilog_include_paths:
tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths))) tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths)))
else: else:
tcl.append("synth_design -top top -part {}".format(platform.device)) tcl.append("synth_design -top {} -part {}".format(build_name, platform.device))
tcl.append("report_timing_summary -file {}_timing_synth.rpt".format(build_name)) tcl.append("report_timing_summary -file {}_timing_synth.rpt".format(build_name))
tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name)) tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name)) tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
......
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