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Kestrel Collaboration
Kestrel LiteX
migen
Commits
9da60e35
Commit
9da60e35
authored
5 years ago
by
Sebastien Bourdeauducq
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sayma_rtm: offer 50T option
parent
fd23e4fb
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-2
migen/build/platforms/sinara/sayma_rtm.py
migen/build/platforms/sinara/sayma_rtm.py
+3
-2
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migen/build/platforms/sinara/sayma_rtm.py
View file @
9da60e35
...
...
@@ -163,8 +163,9 @@ class Platform(XilinxPlatform):
default_clk_name
=
"clk50"
default_clk_period
=
20.0
def
__init__
(
self
):
XilinxPlatform
.
__init__
(
self
,
"xc7a15t-csg325-1"
,
_io
,
_connectors
,
def
__init__
(
self
,
larger
=
False
):
chip
=
"xc7a50t-csg325-1"
if
larger
else
"xc7a15t-csg325-1"
XilinxPlatform
.
__init__
(
self
,
chip
,
_io
,
_connectors
,
toolchain
=
"vivado"
)
self
.
toolchain
.
bitstream_commands
.
extend
([
# FIXME: enable this when the XADC reference wiring is fixed
...
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