Commit f46f014e authored by Florent Kermarrec's avatar Florent Kermarrec
Browse files

fhdl: add simulation Display, Finish support.

In some simulation cases, it's easier to add debug traces directly in the code
than in the verilog/Migen testbench. This adds support for verilog $display in
Migen code.

Being able to terminate a simulation from the code is also useful, this also
add support for verilog $finish.
parent 3d8a5803
......@@ -679,6 +679,7 @@ class Array(list):
else:
return list.__getitem__(self, key)
# clock domains
class ClockDomain:
"""Synchronous domain
......@@ -750,8 +751,21 @@ class _ClockDomainList(list):
return list.__contains__(self, cd_or_name)
# specials
(SPECIAL_INPUT, SPECIAL_OUTPUT, SPECIAL_INOUT) = range(3)
# simulation
class Display(_Statement):
def __init__(self, s, *args):
self.s = s
self.args = args
class Finish(_Statement):
pass
# fragment
class _Fragment:
def __init__(self, comb=None, sync=None, specials=None, clock_domains=None):
......
......@@ -158,6 +158,17 @@ def _printnode(ns, at, level, node):
return r
else:
return ""
elif isinstance(node, Display):
s = "\"" + node.s + "\""
for arg in node.args:
s += ", "
if isinstance(arg, Signal):
s += ns.get_name(arg)
else:
s += str(arg)
return "\t"*level + "$display(" + s + ");\n"
elif isinstance(node, Finish):
return "\t"*level + "$finish;\n"
else:
raise TypeError("Node of unrecognized type: "+str(type(node)))
......
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