Commit be608f95 authored by whitequark's avatar whitequark
Browse files

Revert "lattice/common: no need to differentiate nbits==1 and nbits > 1"

This reverts commit 2dc085d7.

The case of nbits==1 when used with a multi-bit toplevel port results
in generated Verilog similar to:

module top(
  inout [7:0] io,
);

SB_IO #(
  .PIN_TYPE(6'd41)
) SB_IO_21 (
  .D_OUT_0(t_o),
  .OUTPUT_ENABLE(t_oe),
  .PACKAGE_PIN(io[0][0]),
  .D_IN_0(t_i)
);

endmodule

This is not legal as it is not permitted to index into a 1-bit
signal.
parent ac0dd18d
...@@ -86,15 +86,27 @@ class LatticeiCE40AsyncResetSynchronizer: ...@@ -86,15 +86,27 @@ class LatticeiCE40AsyncResetSynchronizer:
class LatticeiCE40TristateImpl(Module): class LatticeiCE40TristateImpl(Module):
def __init__(self, io, o, oe, i): def __init__(self, io, o, oe, i):
nbits, sign = value_bits_sign(io) nbits, sign = value_bits_sign(io)
for bit in range(nbits): if nbits == 1:
# If `io` is an expression like `port[x]`, it is not legal to index further
# into it if it is only 1 bit wide.
self.specials += \ self.specials += \
Instance("SB_IO", Instance("SB_IO",
p_PIN_TYPE=C(0b101001, 6), p_PIN_TYPE=C(0b101001, 6),
io_PACKAGE_PIN=io[bit], io_PACKAGE_PIN=io,
i_OUTPUT_ENABLE=oe, i_OUTPUT_ENABLE=oe,
i_D_OUT_0=o[bit], i_D_OUT_0=o,
o_D_IN_0=i[bit], o_D_IN_0=i,
) )
else:
for bit in range(nbits):
self.specials += \
Instance("SB_IO",
p_PIN_TYPE=C(0b101001, 6),
io_PACKAGE_PIN=io[bit],
i_OUTPUT_ENABLE=oe,
i_D_OUT_0=o[bit],
o_D_IN_0=i[bit],
)
class LatticeiCE40Tristate(Module): class LatticeiCE40Tristate(Module):
......
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