Revert "lattice/common: no need to differentiate nbits==1 and nbits > 1"
This reverts commit 2dc085d7. The case of nbits==1 when used with a multi-bit toplevel port results in generated Verilog similar to: module top( inout [7:0] io, ); SB_IO #( .PIN_TYPE(6'd41) ) SB_IO_21 ( .D_OUT_0(t_o), .OUTPUT_ENABLE(t_oe), .PACKAGE_PIN(io[0][0]), .D_IN_0(t_i) ); endmodule This is not legal as it is not permitted to index into a 1-bit signal.
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