- 29 Apr, 2018 3 commits
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whitequark authored
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whitequark authored
arachne-pnr makes surprising and bad choices when promoting globals.
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whitequark authored
This is useful to avoid glitches at startup e.g. when synchronizing I2C SDA/SCL lines.
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- 27 Apr, 2018 3 commits
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Robert Jordens authored
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Robert Jordens authored
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Robert Jordens authored
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- 25 Apr, 2018 1 commit
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Robert Jordens authored
Apparently nobody has been using it so far. Port directions were wrong. Made it SAME_EDGE to mirror ODDR
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- 17 Apr, 2018 1 commit
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Sebastien Bourdeauducq authored
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- 05 Apr, 2018 2 commits
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Adam Greig authored
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Adam Greig authored
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- 29 Mar, 2018 1 commit
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Sebastien Bourdeauducq authored
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- 28 Mar, 2018 1 commit
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Sebastien Bourdeauducq authored
Does not touch a design that passes timing, and sometimes salvages one that does not.
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- 12 Mar, 2018 1 commit
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Florent Kermarrec authored
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- 09 Mar, 2018 2 commits
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Sebastien Bourdeauducq authored
Prevents warnings (and more?) about CB being driven without a clock buffer.
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Florent Kermarrec authored
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- 07 Mar, 2018 1 commit
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Robert Jordens authored
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- 05 Mar, 2018 2 commits
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Robert Jordens authored
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Robert Jordens authored
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- 02 Mar, 2018 2 commits
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Robert Jordens authored
m-labs/misoc#74
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Robert Jordens authored
* 33 MHz CCLK * QSPI * compress * CFGBVS * CONFIG_VOLTAGE
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- 27 Feb, 2018 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
Migen automatically renames some clock domains (for example in the case of multiple modules defining a clock domain with the same name). When designing, we need in some cases to know the final name of the clock domain and displaying the list of avalaible clock domains helps figuring out what it is. We are using Exception instead of KeyError since KeyError is not able to display on multiple lines.
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- 26 Feb, 2018 1 commit
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Robert Jordens authored
They are pretty big and post-route is usually interesting enough. People can also use post-route to add their own checkpoints.
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- 25 Feb, 2018 1 commit
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Robert Jordens authored
also remove some whitespace
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- 23 Feb, 2018 5 commits
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Robert Jordens authored
* build an easy way for toggling cs to determine HMC830 SPI mode * no miso contention as HMC7043 is three-wire
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
Improves TX data eye from 0.5ns to 1.5ns.
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Sebastien Bourdeauducq authored
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Robert Jordens authored
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- 19 Feb, 2018 1 commit
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Robert Jordens authored
* Clock groups to designate asynchronous clocks is the recommended way (ug903). * This now includes generated clocks (!). And clock groups are bidirectional. * Don't bother creating boolean properties. The design checkpoints don't have them which makes using the latter very hard. String properties are allowed automatically and work fine also in checkpoints. * Use pins to constrain the AsyncResetSynchronizers more precisely.
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- 17 Feb, 2018 1 commit
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Pierre Surply authored
When targeting CPLD devices, Quartus generates the bitstream as a POF file instead of SOF. It is not necessary to convert it to RBF bitstream format in that case. Signed-off-by: Pierre Surply <pierre.surply@lse.epita.fr>
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- 13 Feb, 2018 2 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 26 Jan, 2018 3 commits
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whitequark authored
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Kenneth Ryerson authored
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whitequark authored
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- 23 Jan, 2018 2 commits
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Robert Jordens authored
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Robert Jordens authored
Don't descend the hierarchy into non-migen or external verilog/vhdl entities.
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- 22 Jan, 2018 2 commits
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Robert Jordens authored
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Robert Jordens authored
* more robust than attaching custom attributes to nets which then seem to disappear * less custom attirbutes, more straight forward
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