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Kestrel Collaboration
Kestrel LiteX
migen
Commits
4246d182
Commit
4246d182
authored
6 years ago
by
Robert Jordens
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vivado: multireg are nets, not cells
parent
3a8fe070
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1
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3 deletions
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-3
migen/build/xilinx/vivado.py
migen/build/xilinx/vivado.py
+2
-3
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migen/build/xilinx/vivado.py
View file @
4246d182
...
@@ -92,7 +92,7 @@ class XilinxVivadoToolchain:
...
@@ -92,7 +92,7 @@ class XilinxVivadoToolchain:
def
_build_batch
(
self
,
platform
,
sources
,
build_name
):
def
_build_batch
(
self
,
platform
,
sources
,
build_name
):
tcl
=
[]
tcl
=
[]
tcl
.
append
(
"create_project -force -name {} -part {}"
.
format
(
build_name
,
platform
.
device
))
tcl
.
append
(
"create_project -force -name {} -part {}"
.
format
(
build_name
,
platform
.
device
))
tcl
.
append
(
"create_property -type bool mr_ff
cell
"
)
tcl
.
append
(
"create_property -type bool mr_ff
net
"
)
tcl
.
append
(
"create_property -type bool ars_ff1 cell"
)
tcl
.
append
(
"create_property -type bool ars_ff1 cell"
)
tcl
.
append
(
"create_property -type bool ars_ff2 cell"
)
tcl
.
append
(
"create_property -type bool ars_ff2 cell"
)
for
filename
,
language
,
library
in
sources
:
for
filename
,
language
,
library
in
sources
:
...
@@ -159,8 +159,7 @@ class XilinxVivadoToolchain:
...
@@ -159,8 +159,7 @@ class XilinxVivadoToolchain:
# The asynchronous input to a MultiReg is a false path
# The asynchronous input to a MultiReg is a false path
platform
.
add_platform_command
(
platform
.
add_platform_command
(
"set_false_path -quiet "
"set_false_path -quiet "
"-to [get_pins -filter {{REF_PIN_NAME == D}} -of "
"-to [get_nets -hier -filter mr_ff]]"
"[get_cells -hier -filter {{mr_ff}}]]"
)
)
# The asychronous reset input to the AsyncResetSynchronizer is a false
# The asychronous reset input to the AsyncResetSynchronizer is a false
# path
# path
...
...
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