Commit 3a8fe070 authored by Robert Jordens's avatar Robert Jordens
Browse files

xilinx: find false path inputs using pins

* more robust than attaching custom attributes to nets which then
seem to disappear
* less custom attirbutes, more straight forward
parent 69be2632
...@@ -67,7 +67,6 @@ class XilinxMultiRegImpl(MultiRegImpl): ...@@ -67,7 +67,6 @@ class XilinxMultiRegImpl(MultiRegImpl):
if not hasattr(i, "attr"): if not hasattr(i, "attr"):
i0, i = i, Signal() i0, i = i, Signal()
self.comb += i.eq(i0) self.comb += i.eq(i0)
i.attr.add("mr_false_path")
self.regs[0].attr.add("mr_ff") self.regs[0].attr.add("mr_ff")
for r in self.regs: for r in self.regs:
r.attr.add("async_reg") r.attr.add("async_reg")
...@@ -94,7 +93,6 @@ class XilinxAsyncResetSynchronizerImpl(Module): ...@@ -94,7 +93,6 @@ class XilinxAsyncResetSynchronizerImpl(Module):
i_CE=1, i_C=cd.clk, o_Q=cd.rst, i_CE=1, i_C=cd.clk, o_Q=cd.rst,
attr={"async_reg", "ars_ff2"}) attr={"async_reg", "ars_ff2"})
] ]
async_reset.attr.add("ars_false_path")
class XilinxAsyncResetSynchronizer: class XilinxAsyncResetSynchronizer:
......
...@@ -140,10 +140,8 @@ class XilinxISEToolchain: ...@@ -140,10 +140,8 @@ class XilinxISEToolchain:
"no_retiming": ("register_balancing", "no"), "no_retiming": ("register_balancing", "no"),
"async_reg": None, "async_reg": None,
"mr_ff": None, "mr_ff": None,
"mr_false_path": None,
"ars_ff1": None, "ars_ff1": None,
"ars_ff2": None, "ars_ff2": None,
"ars_false_path": None,
"no_shreg_extract": ("shreg_extract", "no") "no_shreg_extract": ("shreg_extract", "no")
} }
......
...@@ -76,10 +76,8 @@ class XilinxVivadoToolchain: ...@@ -76,10 +76,8 @@ class XilinxVivadoToolchain:
"no_retiming": ("dont_touch", "true"), "no_retiming": ("dont_touch", "true"),
"async_reg": ("async_reg", "true"), "async_reg": ("async_reg", "true"),
"mr_ff": ("mr_ff", "true"), # user-defined attribute "mr_ff": ("mr_ff", "true"), # user-defined attribute
"mr_false_path": ("mr_false_path", "true"), # user-defined attribute
"ars_ff1": ("ars_ff1", "true"), # user-defined attribute "ars_ff1": ("ars_ff1", "true"), # user-defined attribute
"ars_ff2": ("ars_ff2", "true"), # user-defined attribute "ars_ff2": ("ars_ff2", "true"), # user-defined attribute
"ars_false_path": ("ars_false_path", "true"), # user-defined attribute
"no_shreg_extract": None "no_shreg_extract": None
} }
...@@ -95,10 +93,8 @@ class XilinxVivadoToolchain: ...@@ -95,10 +93,8 @@ class XilinxVivadoToolchain:
tcl = [] tcl = []
tcl.append("create_project -force -name {} -part {}".format(build_name, platform.device)) tcl.append("create_project -force -name {} -part {}".format(build_name, platform.device))
tcl.append("create_property -type bool mr_ff cell") tcl.append("create_property -type bool mr_ff cell")
tcl.append("create_property -type bool mr_false_path net")
tcl.append("create_property -type bool ars_ff1 cell") tcl.append("create_property -type bool ars_ff1 cell")
tcl.append("create_property -type bool ars_ff2 cell") tcl.append("create_property -type bool ars_ff2 cell")
tcl.append("create_property -type bool ars_false_path net")
for filename, language, library in sources: for filename, language, library in sources:
filename_tcl = "{" + filename + "}" filename_tcl = "{" + filename + "}"
tcl.append("add_files " + filename_tcl) tcl.append("add_files " + filename_tcl)
...@@ -163,15 +159,15 @@ class XilinxVivadoToolchain: ...@@ -163,15 +159,15 @@ class XilinxVivadoToolchain:
# The asynchronous input to a MultiReg is a false path # The asynchronous input to a MultiReg is a false path
platform.add_platform_command( platform.add_platform_command(
"set_false_path -quiet " "set_false_path -quiet "
"-through [get_nets -hier -filter mr_false_path] " "-to [get_pins -filter {{REF_PIN_NAME == D}} -of "
"-to [get_cells -hier -filter mr_ff]" "[get_cells -hier -filter {{mr_ff}}]]"
) )
# The asychronous reset input to the AsyncResetSynchronizer is a false # The asychronous reset input to the AsyncResetSynchronizer is a false
# path # path
platform.add_platform_command( platform.add_platform_command(
"set_false_path -quiet " "set_false_path -quiet "
"-through [get_nets -hier -filter ars_false_path] " "-to [get_pins -filter {{REF_PIN_NAME == PRE}} -of "
"-to [get_cells -hier -filter {{ars_ff1 || ars_ff2}}]" "[get_cells -hier -filter {{ars_ff1 || ars_ff2}}]]"
) )
# clock_period-2ns to resolve metastability on the wire between the # clock_period-2ns to resolve metastability on the wire between the
# AsyncResetSynchronizer FFs # AsyncResetSynchronizer FFs
......
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