Skip to content
GitLab
Projects
Groups
Snippets
Help
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
Open sidebar
Kestrel Collaboration
Kestrel LiteX
migen
Commits
96f2fa6e
Commit
96f2fa6e
authored
6 years ago
by
Florent Kermarrec
Browse files
Options
Download
Email Patches
Plain Diff
sayma_amc/ddram: use same io constraints than what is used in MIG
parent
90e4101b
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
34 additions
and
28 deletions
+34
-28
migen/build/platforms/sinara/sayma_amc.py
migen/build/platforms/sinara/sayma_amc.py
+34
-28
No files found.
migen/build/platforms/sinara/sayma_amc.py
View file @
96f2fa6e
...
@@ -54,14 +54,14 @@ _io = [
...
@@ -54,14 +54,14 @@ _io = [
Subsignal
(
"a"
,
Pins
(
Subsignal
(
"a"
,
Pins
(
"E15 D15 J16 K18 H16 K17 K16 J15"
,
"E15 D15 J16 K18 H16 K17 K16 J15"
,
"K15 D14 D18 G15 L18 G14 L15"
),
"K15 D14 D18 G15 L18 G14 L15"
),
IOStandard
(
"SSTL15"
)),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"ba"
,
Pins
(
"L19 H17 G16"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"L19 H17 G16"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"ras_n"
,
Pins
(
"E18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"E18"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"cas_n"
,
Pins
(
"E16"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"E16"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"we_n"
,
Pins
(
"D16"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"D16"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"cs_n"
,
Pins
(
"G19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cs_n"
,
Pins
(
"G19"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"dm"
,
Pins
(
"F27 E26 D23 G24"
),
Subsignal
(
"dm"
,
Pins
(
"F27 E26 D23 G24"
),
IOStandard
(
"SSTL15"
),
IOStandard
(
"SSTL15
_DCI
"
),
Misc
(
"DATA_RATE=DDR"
)),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dq"
,
Pins
(
Subsignal
(
"dq"
,
Pins
(
"C28 B27 A27 C27 D28 E28 A28 D29"
,
"C28 B27 A27 C27 D28 E28 A28 D29"
,
...
@@ -72,31 +72,34 @@ _io = [
...
@@ -72,31 +72,34 @@ _io = [
Misc
(
"ODT=RTT_40"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"B29 B24 C21 G20"
),
Subsignal
(
"dqs_p"
,
Pins
(
"B29 B24 C21 G20"
),
IOStandard
(
"DIFF_SSTL15"
),
IOStandard
(
"DIFF_SSTL15_DCI"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"A29 A24 C22 F20"
),
Subsignal
(
"dqs_n"
,
Pins
(
"A29 A24 C22 F20"
),
IOStandard
(
"DIFF_SSTL15"
),
IOStandard
(
"DIFF_SSTL15_DCI"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_p"
,
Pins
(
"J19"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_p"
,
Pins
(
"J19"
),
IOStandard
(
"DIFF_SSTL15
_DCI
"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_n"
,
Pins
(
"J18"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_n"
,
Pins
(
"J18"
),
IOStandard
(
"DIFF_SSTL15
_DCI
"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"cke"
,
Pins
(
"H18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cke"
,
Pins
(
"H18"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"odt"
,
Pins
(
"F19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"F19"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"reset_n"
,
Pins
(
"F14"
),
IOStandard
(
"
LVCMOS
15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"F14"
),
IOStandard
(
"
SSTL
15"
)),
Misc
(
"SLEW=FAST"
),
Misc
(
"SLEW=FAST"
),
Misc
(
"OUTPUT_IMPEDANCE=RDRV_40_40"
)
),
),
(
"ddram_64"
,
0
,
(
"ddram_64"
,
0
,
Subsignal
(
"a"
,
Pins
(
Subsignal
(
"a"
,
Pins
(
"AE17 AL17 AG16 AG17 AD16 AH14 AD15 AK15"
,
"AE17 AL17 AG16 AG17 AD16 AH14 AD15 AK15"
,
"AF14 AF15 AL18 AL15 AE18 AJ15 AG14"
),
"AF14 AF15 AL18 AL15 AE18 AJ15 AG14"
),
IOStandard
(
"SSTL15"
)),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"ba"
,
Pins
(
"AF17 AD19 AD18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"AF17 AD19 AD18"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"ras_n"
,
Pins
(
"AH19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"AH19"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"cas_n"
,
Pins
(
"AK18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"AK18"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"we_n"
,
Pins
(
"AG19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"AG19"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"cs_n"
,
Pins
(
"AF18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cs_n"
,
Pins
(
"AF18"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"dm"
,
Pins
(
"AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"
),
Subsignal
(
"dm"
,
Pins
(
"AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"
),
IOStandard
(
"SSTL15"
),
IOStandard
(
"SSTL15
_DCI
"
),
Misc
(
"DATA_RATE=DDR"
)),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dq"
,
Pins
(
Subsignal
(
"dq"
,
Pins
(
"AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20"
,
"AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20"
,
...
@@ -111,17 +114,20 @@ _io = [
...
@@ -111,17 +114,20 @@ _io = [
Misc
(
"ODT=RTT_40"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"
),
Subsignal
(
"dqs_p"
,
Pins
(
"AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"
),
IOStandard
(
"DIFF_SSTL15"
),
IOStandard
(
"DIFF_SSTL15_DCI"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"
),
Subsignal
(
"dqs_n"
,
Pins
(
"AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"
),
IOStandard
(
"DIFF_SSTL15"
),
IOStandard
(
"DIFF_SSTL15_DCI"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_p"
,
Pins
(
"AE16"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_p"
,
Pins
(
"AE16"
),
IOStandard
(
"DIFF_SSTL15
_DCI
"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_n"
,
Pins
(
"AE15"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_n"
,
Pins
(
"AE15"
),
IOStandard
(
"DIFF_SSTL15
_DCI
"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"cke"
,
Pins
(
"AL19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cke"
,
Pins
(
"AL19"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"odt"
,
Pins
(
"AJ18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"AJ18"
),
IOStandard
(
"SSTL15
_DCI
"
)),
Subsignal
(
"reset_n"
,
Pins
(
"AJ14"
),
IOStandard
(
"
LVCMOS
15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"AJ14"
),
IOStandard
(
"
SSTL
15"
)),
Misc
(
"SLEW=FAST"
),
Misc
(
"SLEW=FAST"
),
Misc
(
"OUTPUT_IMPEDANCE=RDRV_40_40"
)
),
),
(
"eth_clocks"
,
0
,
(
"eth_clocks"
,
0
,
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment