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Kestrel Collaboration
Kestrel LiteX
migen
Commits
40721b28
Commit
40721b28
authored
6 years ago
by
Sebastien Bourdeauducq
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genlib/fifo: add AsyncFIFOBuffered
parent
46b55841
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migen/genlib/fifo.py
migen/genlib/fifo.py
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migen/genlib/fifo.py
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40721b28
...
...
@@ -212,3 +212,22 @@ class AsyncFIFO(Module, _FIFOInterface):
rdport
.
adr
.
eq
(
consume
.
q_next_binary
[:
-
1
]),
self
.
dout
.
eq
(
rdport
.
dat_r
)
]
class
AsyncFIFOBuffered
(
Module
,
_FIFOInterface
):
"""Improves timing when it breaks due to sluggish clock-to-output
delay in e.g. Xilinx block RAMs. Increases latency by one cycle."""
def
__init__
(
self
,
width
,
depth
):
_FIFOInterface
.
__init__
(
self
,
width
,
depth
)
self
.
submodules
.
fifo
=
fifo
=
AsyncFIFO
(
width
,
depth
)
self
.
writable
=
fifo
.
writable
self
.
din
=
fifo
.
din
self
.
we
=
fifo
.
we
self
.
sync
.
read
+=
\
If
(
self
.
re
|
~
self
.
readable
,
self
.
dout
.
eq
(
fifo
.
dout
),
self
.
readable
.
eq
(
fifo
.
readable
)
)
self
.
comb
+=
fifo
.
re
.
eq
(
self
.
re
|
~
self
.
readable
)
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