Commit f4180e9c authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
Browse files

vivado: print short timing info after phys_opt_design

parent c65a2f38
......@@ -119,6 +119,7 @@ class XilinxVivadoToolchain:
tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
tcl.append("route_design")
tcl.append("phys_opt_design")
tcl.append("report_timing_summary -no_header -no_detailed_paths")
tcl.append("write_checkpoint -force {}_route.dcp".format(build_name))
tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
tcl.append("report_drc -file {}_drc.rpt".format(build_name))
......
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