- 06 May, 2021 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
clarity on configuration.
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- 13 Apr, 2021 1 commit
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Raptor Engineering Development Team authored
The existing VUART interrupt handler did not function as intended. Rewrite to match the hardware interfaces.
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- 02 Apr, 2021 2 commits
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Raptor Engineering Development Team authored
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Jonathan Currier authored
Note that this embeds a power limit, which may be board/system specific.
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- 27 Mar, 2021 2 commits
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Raptor Engineering Development Team authored
This resolves issues where the #ifdef-controlled code could counter-intuitively be activated even when the controlling #define statement was set to 0.
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Raptor Engineering Development Team authored
This optional debug mode will attempt to read each Flash chunk three times, comparing all three read values to determine if bus instability exists. This mode is slower than a straight read, but is useful in initial bringup of new hardware designs or when modifying the SPI core HDL and for CI/CD checks.
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- 21 Mar, 2021 2 commits
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Evan Lojewski authored
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Raptor Engineering Development Team authored
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- 20 Mar, 2021 11 commits
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Raptor Engineering Development Team authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
- Add common routines for cpu0/cpu1 - Wrap CPU1 code in #ifdef I3CMASTER2_BASE in teh event that the FPGA was not build with the additioanl i2c master.
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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- 28 Jan, 2021 1 commit
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Raptor Engineering Development Team authored
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- 15 Jan, 2021 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
Major update Verified to fully IPL attached Blackbird host to Petitboot shell using Versa ECP5
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- 28 Jun, 2020 1 commit
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Raptor Engineering Development Team authored
Do not attempt merged Flashed read/writes during 32-bit CPU accesses in non-merged mode Split Kestrel SPI defines into dedicated header
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- 26 Jun, 2020 1 commit
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Raptor Engineering Development Team authored
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- 15 Jun, 2020 2 commits
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Raptor Engineering Development Team authored
Add initial integration of FSI core and FSI IPL firmware for Raptor Computing Systems POWER9 systems Verified to properly start the IPL sequence on a Raptor Computing Systems Blackbird with external LPC / IPMI bridge interface attached.
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Raptor Engineering Development Team authored
Cloned from litex-hub/fpga_101/lab004/firmware, and all demo-specific display / LED test functionality removed. Per the author, _florent_, on Freenode IRC 06/14/2020, this basic code is provided without any copyright restrictions.
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