Adjust SPI Flash clock speed to compensate for main bus speed reduction from 75MHz to 50MHz

860658c1 · Raptor Engineering Development Team · 066b0159 · 860658c1
Commit 860658c1 authored Mar 20, 2021 by Raptor Engineering Development Team
Hide whitespace changes
Inline Side-by-side

Showing with 2 additions and 2 deletions

main.c main.c +2 -2

No files found.
--- a/main.c
+++ b/main.c
@@ -2383,10 +2383,10 @@ static int host_spi_flash_init(void)
    dword |= ((TERCEL_SPI_PHY_IO_TYPE_QUAD & TERCEL_SPI_PHY_IO_TYPE_MASK) << TERCEL_SPI_PHY_IO_TYPE_SHIFT);
    write_tercel_register(HOSTSPIFLASHCFG_BASE, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);

-    // Set SPI clock cycle divider to 8
+    // Set SPI clock cycle divider to 5
    dword = read_tercel_register(HOSTSPIFLASHCFG_BASE, TERCEL_SPI_REG_SYS_PHY_CFG1);
    dword &= ~(TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK << TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT);
-    dword |= ((8 & TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK) << TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT);
+    dword |= ((5 & TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK) << TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT);
    write_tercel_register(HOSTSPIFLASHCFG_BASE, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);

    // Calculate and dump configured SPI clock speed