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Try the more widely used 0x9f ID command first, then fall back to
the Micron-preferred 0x9e command if that fails.

Automatically soft-enable Flash writes when Flash writes
allowed by build configuration.

Don't attempt to set QSPI control bits when QSPI mode is
disabled.

Since the uptime counter is updated in an ISR, the compiler may
attempt to optimize away code that checks for an updated value.

Avoid this by marking the uptime counter as volatile.

This adds functionality currently present in the ASpeed
BMC firmware stack.

Increase SPI frequency to maximum possible

This works around instability seen on some firmware loads,
which can cause Flash corruption.  Once the timing failures
in the QSPI controller place/route process are resolved,
QSPI mode should be re-enabled.

Add basic 1ms system timer service

This fixes crashes caused by stack overflow during simultaneous
operations with the host console service running

Fix up console help text

Read all relevant early IPL registers and
decode as part of sbe_status command.

This resolves display corruption observed in / after
complex printf() statements.

clarity on configuration.

The existing VUART interrupt handler did not function
as intended.  Rewrite to match the hardware interfaces.

FSI interface seems stable at this point, and the debug spew to
console is not particularly useful for future development of the
BMC firmware.

Note that this embeds a power limit, which may be board/system specific.

This resolves IPL failures with the current FPGA images

This resolves issues where the #ifdef-controlled code could
counter-intuitively be activated even when the controlling #define
statement was set to 0.

This optional debug mode will attempt to read each Flash chunk three
times, comparing all three read values to determine if bus instability
exists.  This mode is slower than a straight read, but is useful in
initial bringup of new hardware designs or when modifying the SPI
core HDL and for CI/CD checks.

This updates the jenkins configuration to match the recommendations from
https://github.com/jenkinsci/gitlab-plugin

- Add common routines for cpu0/cpu1
- Wrap CPU1 code in #ifdef I3CMASTER2_BASE in teh event that the FPGA was not build with the additioanl i2c master.