- 06 May, 2021 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
clarity on configuration.
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- 17 Apr, 2021 1 commit
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Evan Lojewski authored
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- 13 Apr, 2021 1 commit
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Raptor Engineering Development Team authored
The existing VUART interrupt handler did not function as intended. Rewrite to match the hardware interfaces.
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- 02 Apr, 2021 3 commits
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Raptor Engineering Development Team authored
FSI interface seems stable at this point, and the debug spew to console is not particularly useful for future development of the BMC firmware.
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Raptor Engineering Development Team authored
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Jonathan Currier authored
Note that this embeds a power limit, which may be board/system specific.
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- 30 Mar, 2021 1 commit
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Raptor Engineering Development Team authored
This resolves IPL failures with the current FPGA images
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- 27 Mar, 2021 6 commits
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Raptor Engineering Development Team authored
This resolves issues where the #ifdef-controlled code could counter-intuitively be activated even when the controlling #define statement was set to 0.
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Raptor Engineering Development Team authored
This optional debug mode will attempt to read each Flash chunk three times, comparing all three read values to determine if bus instability exists. This mode is slower than a straight read, but is useful in initial bringup of new hardware designs or when modifying the SPI core HDL and for CI/CD checks.
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- 26 Mar, 2021 1 commit
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Evan Lojewski authored
This updates the jenkins configuration to match the recommendations from https://github.com/jenkinsci/gitlab-plugin
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- 21 Mar, 2021 5 commits
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Evan Lojewski authored
bootrom: Revup bootrom submodule See merge request kestrel-collaboration/kestrel-firmware/bare-metal-firmware!1
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Evan Lojewski authored
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Evan Lojewski authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 20 Mar, 2021 16 commits
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Raptor Engineering Development Team authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
- Add common routines for cpu0/cpu1 - Wrap CPU1 code in #ifdef I3CMASTER2_BASE in teh event that the FPGA was not build with the additioanl i2c master.
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Evan Lojewski authored
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Evan Lojewski authored
- Fix description for 64MB flash chips to be 512Mb not 512MB - Add Support for the 128MB flash chips
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Evan Lojewski authored
Previously, back to back FSI transactions could happen before teh FSI state machine was complete. This ensures that the FSI master does not ahve an active transaction before starting a new one. This could result in logs such as: access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001 access_fsi_mem(): address 0x002804, data: 0x00000000 sta: 0x12000000 vs access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001 access_fsi_mem(): address 0x002804, data: 0x04c04000 sta: 0x41000001 As a result, the CPU often failed to start.
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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- 28 Jan, 2021 1 commit
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Raptor Engineering Development Team authored
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- 15 Jan, 2021 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
Major update Verified to fully IPL attached Blackbird host to Petitboot shell using Versa ECP5
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- 28 Jun, 2020 1 commit
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Raptor Engineering Development Team authored
Do not attempt merged Flashed read/writes during 32-bit CPU accesses in non-merged mode Split Kestrel SPI defines into dedicated header
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