Skip to content

B
Bare Metal Firmware
Commit 5ededa77 authored by Raptor Engineering Development Team's avatar Raptor Engineering Development Team
Browse files
Options

Rework VUART interrupt handler 

The existing VUART interrupt handler did not function
as intended.  Rewrite to match the hardware interfaces.
parent 1cb45069
Pipeline #195 passed with stage
    in 18 seconds
    Hide whitespace changes
    Inline Side-by-side
    Showing with 39 additions and 38 deletions
    aquila.h
    View file @ 5ededa77
    ......@@ -107,8 +107,9 @@
    #define AQUILA_LPC_IPMI_BT_DATA_BLOCK_OFFSET 0xd00000
    #define AQUILA_LPC_STATUS_CYCLE_TYPE_IO 0
    #define AQUILA_LPC_STATUS_CYCLE_TYPE_FW 2
    #define AQUILA_LPC_STATUS_CYCLE_TYPE_IO 0
    #define AQUILA_LPC_STATUS_CYCLE_TYPE_TPM 1
    #define AQUILA_LPC_STATUS_CYCLE_TYPE_FW 2
    #define AQUILA_LPC_VUART1_FIFO_EMPTY 0x00000100
    #define AQUILA_LPC_VUART2_FIFO_EMPTY 0x01000000
    ......@@ -123,10 +124,14 @@
    #define AQUILA_LPC_VUART1_FIFO_READ_MASK 0xff
    #define AQUILA_LPC_VUART1_FIFO_READ_SHIFT 0
    #define AQUILA_LPC_VUART2_FIFO_READ_MASK 0xff
    #define AQUILA_LPC_VUART2_FIFO_READ_SHIFT 16
    #define AQUILA_LPC_VUART_BLOCK_OFFSET 0xe00000
    #define AQUILA_LPC_VUART1_STATUS_REG 0x4
    #define AQUILA_LPC_VUART1_CONTROL_REG 0x8
    #define AQUILA_LPC_VUART2_STATUS_REG 0xc
    #define AQUILA_LPC_VUART2_CONTROL_REG 0x10
    #define AQUILA_LPC_VUART_FIFO_TRIG_LVL_MASK 0xff
    #define AQUILA_LPC_VUART_FIFO_TRIG_LVL_SHIFT 8
    #define AQUILA_LPC_VUART_FIFO_IRQ_EN_MASK 0x1
    ......
    main.c
    View file @ 5ededa77
    ......@@ -452,51 +452,47 @@ void lpc_slave_isr(void)
    }
    }
    #endif
    if (status4_reg & AQUILA_LPC_VUART1_IRQ_ASSERTED)
    if ((status4_reg & AQUILA_LPC_VUART1_IRQ_ASSERTED) || (status4_reg & AQUILA_LPC_VUART2_IRQ_ASSERTED))
    {
    // VUART1 has asserted its IRQ
    // VUART1 or VUART2 has asserted its IRQ
    // Copy received characters to IRQ receive buffer
    do
    {
    vuart_status = *((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + 0x0));
    vuart1_incoming_interrupt_transient_buffer[vuart1_incoming_interrupt_transient_buffer_pos] =
    (vuart_status >> AQUILA_LPC_VUART1_FIFO_READ_SHIFT) & AQUILA_LPC_VUART1_FIFO_READ_MASK;
    vuart1_incoming_interrupt_transient_buffer_pos++;
    if (vuart1_incoming_interrupt_transient_buffer_pos >= VUART_INTERRUPT_TRANSIENT_BUFFER_SIZE)
    if (!(vuart_status & AQUILA_LPC_VUART1_FIFO_EMPTY))
    {
    // Transient buffer is full
    // Disable VUART1 interrupts, since we are no longer able to service
    // them, then exit the copy routine
    dword = (*((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + AQUILA_LPC_VUART1_CONTROL_REG)));
    dword &= ~((1 & AQUILA_LPC_VUART_IRQ_EN_MASK) << AQUILA_LPC_VUART_IRQ_EN_SHIFT);
    (*((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + AQUILA_LPC_VUART1_CONTROL_REG))) = dword;
    vuart1_incoming_interrupt_transient_buffer_overflow = 1;
    break;
    vuart1_incoming_interrupt_transient_buffer[vuart1_incoming_interrupt_transient_buffer_pos] =
    (vuart_status >> AQUILA_LPC_VUART1_FIFO_READ_SHIFT) & AQUILA_LPC_VUART1_FIFO_READ_MASK;
    vuart1_incoming_interrupt_transient_buffer_pos++;
    if (vuart1_incoming_interrupt_transient_buffer_pos >= VUART_INTERRUPT_TRANSIENT_BUFFER_SIZE)
    {
    // Transient buffer is full
    // Disable VUART1 interrupts, since we are no longer able to service
    // them, then exit the copy routine
    dword = (*((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + AQUILA_LPC_VUART1_CONTROL_REG)));
    dword &= ~((1 & AQUILA_LPC_VUART_IRQ_EN_MASK) << AQUILA_LPC_VUART_IRQ_EN_SHIFT);
    (*((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + AQUILA_LPC_VUART1_CONTROL_REG))) = dword;
    vuart1_incoming_interrupt_transient_buffer_overflow = 1;
    }
    }
    } while (!(vuart_status & AQUILA_LPC_VUART1_FIFO_EMPTY));
    }
    if (status4_reg & AQUILA_LPC_VUART2_IRQ_ASSERTED)
    {
    // VUART2 has asserted its IRQ
    // Copy received characters to IRQ receive buffer
    do
    {
    vuart_status = *((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + 0x0));
    vuart2_incoming_interrupt_transient_buffer[vuart2_incoming_interrupt_transient_buffer_pos] =
    (vuart_status >> AQUILA_LPC_VUART1_FIFO_READ_SHIFT) & AQUILA_LPC_VUART1_FIFO_READ_MASK;
    vuart2_incoming_interrupt_transient_buffer_pos++;
    if (vuart2_incoming_interrupt_transient_buffer_pos >= VUART_INTERRUPT_TRANSIENT_BUFFER_SIZE)
    if (!(vuart_status & AQUILA_LPC_VUART2_FIFO_EMPTY))
    {
    // Transient buffer is full
    // Disable VUART2 interrupts, since we are no longer able to service
    // them, then exit the copy routine
    dword = (*((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + AQUILA_LPC_VUART1_CONTROL_REG)));
    dword &= ~((1 & AQUILA_LPC_VUART_IRQ_EN_MASK) << AQUILA_LPC_VUART_IRQ_EN_SHIFT);
    (*((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + AQUILA_LPC_VUART1_CONTROL_REG))) = dword;
    vuart2_incoming_interrupt_transient_buffer_overflow = 1;
    break;
    vuart2_incoming_interrupt_transient_buffer[vuart2_incoming_interrupt_transient_buffer_pos] =
    (vuart_status >> AQUILA_LPC_VUART2_FIFO_READ_SHIFT) & AQUILA_LPC_VUART2_FIFO_READ_MASK;
    vuart2_incoming_interrupt_transient_buffer_pos++;
    if (vuart2_incoming_interrupt_transient_buffer_pos >= VUART_INTERRUPT_TRANSIENT_BUFFER_SIZE)
    {
    // Transient buffer is full
    // Disable VUART2 interrupts, since we are no longer able to service
    // them, then exit the copy routine
    dword = (*((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + AQUILA_LPC_VUART2_CONTROL_REG)));
    dword &= ~((1 & AQUILA_LPC_VUART_IRQ_EN_MASK) << AQUILA_LPC_VUART_IRQ_EN_SHIFT);
    (*((volatile uint32_t *)(HOSTLPCSLAVE_BASE + AQUILA_LPC_VUART_BLOCK_OFFSET + AQUILA_LPC_VUART2_CONTROL_REG))) = dword;
    vuart2_incoming_interrupt_transient_buffer_overflow = 1;
    }
    }
    } while (!(vuart_status & AQUILA_LPC_VUART1_FIFO_EMPTY));
    } while (((!(vuart_status & AQUILA_LPC_VUART1_FIFO_EMPTY)) && (!vuart1_incoming_interrupt_transient_buffer_overflow)) ||
    ((!(vuart_status & AQUILA_LPC_VUART2_FIFO_EMPTY)) && (!vuart2_incoming_interrupt_transient_buffer_overflow)));
    }
    if (status4_reg & AQUILA_LPC_IPMI_BT_IRQ_ASSERTED)
    {
    ......
    Markdown is supported
    0% or
    You are about to add 0 people to the discussion. Proceed with caution.
    Finish editing this message first!
    Please register or to comment

    Powered by Integricloud