- 15 Jun, 2018 2 commits
-
-
Robert Jördens authored
-
Robert Jördens authored
-
- 13 Jun, 2018 3 commits
-
-
Sebastien Bourdeauducq authored
-
Sebastien Bourdeauducq authored
-
Sebastien Bourdeauducq authored
-
- 12 Jun, 2018 1 commit
-
-
Robert Jördens authored
-
- 10 Jun, 2018 1 commit
-
-
Robert Jördens authored
verilog 2001 4.5.1
-
- 06 Jun, 2018 1 commit
-
-
Florent Kermarrec authored
-
- 05 Jun, 2018 1 commit
-
-
Florent Kermarrec authored
revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers
-
- 04 Jun, 2018 1 commit
-
-
Florent Kermarrec authored
genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers
-
- 30 May, 2018 1 commit
-
-
whitequark authored
-
- 28 May, 2018 1 commit
-
-
whitequark authored
-
- 25 May, 2018 1 commit
-
-
whitequark authored
-
- 17 May, 2018 2 commits
-
-
William D. Jones authored
-
William D. Jones authored
-
- 15 May, 2018 1 commit
-
-
Florent Kermarrec authored
-
- 02 May, 2018 2 commits
-
-
whitequark authored
-
whitequark authored
This causes warnings when synthesizing with Yosys.
-
- 29 Apr, 2018 3 commits
-
-
whitequark authored
-
whitequark authored
arachne-pnr makes surprising and bad choices when promoting globals.
-
whitequark authored
This is useful to avoid glitches at startup e.g. when synchronizing I2C SDA/SCL lines.
-
- 27 Apr, 2018 3 commits
-
-
Robert Jordens authored
-
Robert Jordens authored
-
Robert Jordens authored
-
- 25 Apr, 2018 1 commit
-
-
Robert Jordens authored
Apparently nobody has been using it so far. Port directions were wrong. Made it SAME_EDGE to mirror ODDR
-
- 17 Apr, 2018 1 commit
-
-
Sebastien Bourdeauducq authored
-
- 05 Apr, 2018 2 commits
-
-
Adam Greig authored
-
Adam Greig authored
-
- 29 Mar, 2018 1 commit
-
-
Sebastien Bourdeauducq authored
-
- 28 Mar, 2018 1 commit
-
-
Sebastien Bourdeauducq authored
Does not touch a design that passes timing, and sometimes salvages one that does not.
-
- 12 Mar, 2018 1 commit
-
-
Florent Kermarrec authored
-
- 09 Mar, 2018 2 commits
-
-
Sebastien Bourdeauducq authored
Prevents warnings (and more?) about CB being driven without a clock buffer.
-
Florent Kermarrec authored
-
- 07 Mar, 2018 1 commit
-
-
Robert Jordens authored
-
- 05 Mar, 2018 2 commits
-
-
Robert Jordens authored
-
Robert Jordens authored
-
- 02 Mar, 2018 2 commits
-
-
Robert Jordens authored
m-labs/misoc#74
-
Robert Jordens authored
* 33 MHz CCLK * QSPI * compress * CFGBVS * CONFIG_VOLTAGE
-
- 27 Feb, 2018 2 commits
-
-
Florent Kermarrec authored
-
Florent Kermarrec authored
Migen automatically renames some clock domains (for example in the case of multiple modules defining a clock domain with the same name). When designing, we need in some cases to know the final name of the clock domain and displaying the list of avalaible clock domains helps figuring out what it is. We are using Exception instead of KeyError since KeyError is not able to display on multiple lines.
-